| /openbmc/qemu/include/hw/intc/ |
| H A D | arm_gic.h | 24 * + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
32 * [P..P+31] PPIs for CPU 0
33 * [P+32..P+63] PPIs for CPU 1
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| H A D | arm_gic_common.h | 29 /* First 32 are private to each CPU (SGIs and PPIs). */
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| H A D | arm_gicv3_common.h | 62 * space for the PPIs and SGIs, those bits (the first 32) are never
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| /openbmc/linux/drivers/perf/ |
| H A D | arm_pmu_acpi.c | 49 * a fixed value in HW (for both SPIs and PPIs) that we cannot change in arm_pmu_acpi_register_irq()
238 * corresponding GSI once (e.g. when we have PPIs). in arm_pmu_acpi_parse_irqs()
268 * the PMU (e.g. we don't have mismatched PPIs).
288 pr_warn("mismatched PPIs detected\n"); in pmu_irq_matches()
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| H A D | arm_pmu_platform.c | 134 dev_warn(dev, "multiple PPIs or mismatched SPI/PPI detected\n"); in pmu_parse_irqs()
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| /openbmc/u-boot/arch/arm/lib/ |
| H A D | gic_64.S | 106 str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
140 * Initialize SGIs and PPIs
144 mov w9, #~0 /* Config SGIs and PPIs as Grp1 */
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| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3_dist.c | 100 * RAZ/WI for SGIs, PPIs, unimplemented IRQs in gicd_write_bitmap_reg()
123 * RAZ/WI for SGIs, PPIs, unimplemented IRQs in gicd_write_set_bitmap_reg()
147 * RAZ/WI for SGIs, PPIs, unimplemented IRQs in gicd_write_clear_bitmap_reg()
171 * RAZ/WI for SGIs, PPIs, unimplemented IRQs in gicd_read_bitmap_reg()
454 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ in gicd_readl()
536 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ in gicd_readl()
662 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ in gicd_writel()
749 /* RAZ/WI for SGIs, PPIs, unimplemented irqs */ in gicd_writel()
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| H A D | arm_gic_common.c | 138 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. in gic_init_irqs_and_mmio()
141 * [N..N+31] PPIs for CPU 0 in gic_init_irqs_and_mmio()
142 * [N+32..N+63] PPIs for CPU 1 in gic_init_irqs_and_mmio()
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| H A D | arm_gicv3_common.c | 318 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. in gicv3_init_irqs_and_mmio()
321 * [N..N+31] PPIs for CPU 0 in gicv3_init_irqs_and_mmio()
322 * [N+32..N+63] PPIs for CPU 1 in gicv3_init_irqs_and_mmio()
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | ti,omap4-wugen-mpu | 20 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
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| H A D | arm,gic.yaml | 17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
19 have PPIs or SGIs.
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| H A D | nvidia,tegra20-ictlr.txt | 27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
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| H A D | arm,gic-v3.yaml | 63 interrupt types other than PPI or PPIs that are not partitionned,
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | gic.h | 71 /* ReDistributor Registers for SGIs and PPIs */
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| /openbmc/linux/drivers/acpi/arm64/ |
| H A D | gtdt.c | 86 * acpi_gtdt_map_ppi() - Map the PPIs of per-cpu arch_timer.
90 * So we only handle the non-secure timer PPIs,
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | arm,arch_timer.yaml | 18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
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| /openbmc/linux/drivers/clocksource/ |
| H A D | timer-mediatek-cpux.c | 87 * on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ.
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| /openbmc/linux/arch/arm64/kvm/vgic/ |
| H A D | vgic-init.c | 209 * configure all PPIs as level-triggered. in kvm_vgic_vcpu_init()
225 /* PPIs */ in kvm_vgic_vcpu_init()
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| H A D | vgic.c | 95 /* SGIs and PPIs */ in vgic_get_irq()
425 * @cpuid: The CPU for PPIs
596 * @vcpu: Pointer to the VCPU (used for PPIs)
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| /openbmc/linux/arch/arm64/kvm/ |
| H A D | arch_timer.c | 1454 u32 ppis = 0; in timer_irqs_are_valid() local
1469 * We know by construction that we only have PPIs, so in timer_irqs_are_valid()
1472 ppis |= BIT(irq); in timer_irqs_are_valid()
1475 valid = hweight32(ppis) == nr_timers(vcpu); in timer_irqs_are_valid()
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| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-xgene-sb.c | 195 /* Skip SGIs and PPIs*/ in xgene_gpio_sb_domain_alloc()
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| /openbmc/linux/tools/testing/selftests/kvm/lib/aarch64/ |
| H A D | gic_v3.c | 308 /* Set a default priority for all the SGIs and PPIs */ in gicv3_cpu_init()
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-hip04.c | 135 /* Misconfigured PPIs are usually not fatal */ in hip04_irq_set_type()
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| /openbmc/linux/tools/testing/selftests/kvm/aarch64/ |
| H A D | vgic_irq.c | 103 /* can inject PPIs, PPIs, and/or SPIs. */
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| /openbmc/linux/include/kvm/ |
| H A D | arm_vgic.h | 122 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
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