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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
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H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
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H A Dfsl,qoriq-mc-dpmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
17 - $ref: ethernet-controller.yaml#
21 const: fsl,qoriq-mc-dpmac
27 phy-handle: true
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H A Dfsl,fman-dtsec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
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/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include "phy-qcom-qmp-qserdes-com.h"
10 #include "phy-qcom-qmp-qserdes-txrx.h"
12 #include "phy-qcom-qmp-qserdes-com-v3.h"
13 #include "phy-qcom-qmp-qserdes-txrx-v3.h"
15 #include "phy-qcom-qmp-qserdes-com-v4.h"
16 #include "phy-qcom-qmp-qserdes-txrx-v4.h"
17 #include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
19 #include "phy-qcom-qmp-qserdes-com-v5.h"
20 #include "phy-qcom-qmp-qserdes-txrx-v5.h"
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H A Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-ufs-v2.h"
25 #include "phy-qcom-qmp-pcs-ufs-v3.h"
26 #include "phy-qcom-qmp-pcs-ufs-v4.h"
27 #include "phy-qcom-qmp-pcs-ufs-v5.h"
28 #include "phy-qcom-qmp-pcs-ufs-v6.h"
30 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
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H A Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include "phy-qcom-qmp.h"
66 /* set of registers with offsets different per-PHY */
73 /* PCS registers */
169 /* struct qmp_phy_cfg - per-PHY initialization config */
174 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
199 * struct qmp_phy - per-lane phy descriptor
201 * @phy: generic phy
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H A Dphy-qcom-qmp-usb-legacy.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include <linux/phy/phy.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
39 /* DP PHY soft reset */
41 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
43 /* USB3 PHY soft reset */
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H A Dphy-qcom-qmp-pcie.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include <linux/phy/pcie.h>
18 #include <linux/phy/phy.h>
25 #include "phy-qcom-qmp.h"
26 #include "phy-qcom-qmp-pcs-misc-v3.h"
27 #include "phy-qcom-qmp-pcs-pcie-v4.h"
28 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
29 #include "phy-qcom-qmp-pcs-pcie-v5.h"
30 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
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H A Dphy-qcom-qmp-usb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include "phy-qcom-qmp.h"
23 #include "phy
1153 u16 pcs; global() member
1207 void __iomem *pcs; global() member
1222 struct phy *phy; global() member
1654 qmp_usb_init(struct phy * phy) qmp_usb_init() argument
1658 void __iomem *pcs = qmp->pcs; qmp_usb_init() local
1695 qmp_usb_exit(struct phy * phy) qmp_usb_exit() argument
1709 qmp_usb_power_on(struct phy * phy) qmp_usb_power_on() argument
1715 void __iomem *pcs = qmp->pcs; qmp_usb_power_on() local
1768 qmp_usb_power_off(struct phy * phy) qmp_usb_power_off() argument
1789 qmp_usb_enable(struct phy * phy) qmp_usb_enable() argument
1804 qmp_usb_disable(struct phy * phy) qmp_usb_disable() argument
1814 qmp_usb_set_mode(struct phy * phy,enum phy_mode mode,int submode) qmp_usb_set_mode() argument
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/openbmc/linux/drivers/net/phy/
H A Dphylink.c1 // SPDX-License-Identifier: GPL-2.0
3 * phylink models the MAC to optional PHY connection, supporting
4 * technologies such as SFP cages where the PHY is hot-pluggable.
15 #include <linux/phy.h>
44 * struct phylink - internal data type for phylink
51 struct phylink_pcs *pcs; member
60 u8 link_port; /* The current non-phy ethtool port */
93 if ((pl)->config->type == PHYLINK_NETDEV) \
94 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
95 else if ((pl)->config->type == PHYLINK_DEV) \
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/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
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H A Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
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/openbmc/linux/include/linux/
H A Dphylink.h4 #include <linux/phy.h>
21 MLO_AN_PHY = 0, /* Conventional PHY */
22 MLO_AN_FIXED, /* Fixed-link mode */
23 MLO_AN_INBAND, /* In-band protocol */
25 /* PCS "negotiation" mode.
26 * PHYLINK_PCS_NEG_NONE - protocol has no inband capability
27 * PHYLINK_PCS_NEG_OUTBAND - some out of band or fixed link setting
28 * PHYLINK_PCS_NEG_INBAND_DISABLED - inband mode disabled, e.g.
29 * 1000base-X with autoneg off
30 * PHYLINK_PCS_NEG_INBAND_ENABLED - inband mode enabled
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/openbmc/linux/drivers/net/fddi/skfp/
H A Dpcmplc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
67 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
68 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
109 * PCL-S control register
110 * this register in the PLC-S controls the scrambling parameters
121 * PCL-S control register
122 * this register in the PLC-S controls the scrambling parameters
152 #define PLC_MS(m) ((int)((0x10000L-(m*100000L/2048))))
191 static void pcm_fsm(struct s_smc *smc, struct s_phy *phy, int cmd);
192 static void pc_rcode_actions(struct s_smc *smc, int bit, struct s_phy *phy);
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/openbmc/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_phylink.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/phy/phy.h>
14 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_select()
16 return &port->phylink_pcs; in lan966x_phylink_mac_select()
29 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_prepare()
33 if (port->serdes) { in lan966x_phylink_mac_prepare()
34 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, in lan966x_phylink_mac_prepare()
37 netdev_err(to_net_dev(config->dev), in lan966x_phylink_mac_prepare()
47 struct phy_device *phy, in lan966x_phylink_mac_link_up() argument
53 struct lan966x_port *port = netdev_priv(to_net_dev(config->dev)); in lan966x_phylink_mac_link_up()
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/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Marvell 88E6352 family SERDES PCS support
15 #include "phy.h"
35 err = mdiodev_c45_read(&mpcs->mdio, MDIO_MMD_PHYXS, regnum); in mv88e639x_read()
46 return mdiodev_c45_write(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, val); in mv88e639x_write()
52 return mdiodev_c45_modify(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, mask, in mv88e639x_modify()
59 return mdiodev_c45_modify_changed(&mpcs->mdio, MDIO_MMD_PHYXS, regnum, in mv88e639x_modify_changed()
73 mpcs->mdio.dev.parent = dev; in mv88e639x_pcs_alloc()
74 mpcs->mdio.bus = bus; in mv88e639x_pcs_alloc()
75 mpcs->mdio.addr = addr; in mv88e639x_pcs_alloc()
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/openbmc/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpaa2-mac.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 #include <linux/pcs-lynx.h>
6 #include <linux/phy/phy.h>
9 #include "dpaa2-eth.h"
10 #include "dpaa2-mac.h"
23 if (mac->ver_major == ver_major) in dpaa2_mac_cmp_ver()
24 return mac->ver_minor - ver_minor; in dpaa2_mac_cmp_ver()
25 return mac->ver_major - ver_major; in dpaa2_mac_cmp_ver()
30 mac->features = 0; in dpaa2_mac_detect_features()
34 mac->features |= DPAA2_MAC_FEATURE_PROTOCOL_CHANGE; in dpaa2_mac_detect_features()
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
13 set PCS delay value.
14 e.g. PCIE PHY in DRA7x
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/openbmc/linux/drivers/net/dsa/b53/
H A Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Northstar Plus switch SerDes/SGMII PHY main logic
12 #include <linux/phy.h>
20 static inline struct b53_pcs *pcs_to_b53_pcs(struct phylink_pcs *pcs) in pcs_to_b53_pcs() argument
22 return container_of(pcs, struct b53_pcs, pcs); in pcs_to_b53_pcs()
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
68 static int b53_serdes_config(struct phylink_pcs *pcs, unsigned int neg_mode, in b53_serdes_config() argument
73 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_config()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config()
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/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Drenesas,rzn1-a5psw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <clement.leger@bootlin.com>
17 - $ref: dsa.yaml#/$defs/ethernet-ports
22 - enum:
23 - renesas,r9a06g032-a5psw
24 - const: renesas,rzn1-a5psw
31 - description: Device Level Ring (DLR) interrupt
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/openbmc/linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
H A Dmac-phy-support.rst1 .. SPDX-License-Identifier: GPL-2.0
5 DPAA2 MAC / PHY support
11 --------
13 The DPAA2 MAC / PHY support consists of a set of APIs that help DPAA2 network
14 drivers (dpaa2-eth, dpaa2-ethsw) interact with the PHY library.
17 ---------------------------
19 Among other DPAA2 objects, the fsl-mc bus exports DPNI objects (abstracting a
20 network interface) and DPMAC objects (abstracting a MAC). The dpaa2-eth driver
26 directly by the dpaa2-eth driver or by phylink.
28 .. code-block:: none
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/openbmc/linux/include/uapi/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
22 #define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
51 #define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
58 /* Media-dependent registers. */
59 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
60 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
61 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
62 * Lanes B-D are numbered 134-136. */
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-socfpga.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Adopted from dwmac-sti.c
7 #include <linux/mfd/altera-sysmgr.h>
11 #include <linux/phy.h>
13 #include <linux/mdio/mdio-regmap.h>
14 #include <linux/pcs-lynx.h>
67 void __iomem *splitter_base = dwmac->splitter_base; in socfpga_dwmac_fix_mac_speed()
68 void __iomem *sgmii_adapter_base = dwmac->sgmii_adapter_base; in socfpga_dwmac_fix_mac_speed()
69 struct device *dev = dwmac->dev; in socfpga_dwmac_fix_mac_speed()
71 struct phy_device *phy_dev = ndev->phydev; in socfpga_dwmac_fix_mac_speed()
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