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/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c20 #include <asm/arch/pch.h>
29 static int pch_enable_apic(struct udevice *pch) in pch_enable_apic() argument
35 dm_pci_write_config8(pch, ACPI_CNTL, 0x80); in pch_enable_apic()
48 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); in pch_enable_apic()
71 static void pch_enable_serial_irqs(struct udevice *pch) in pch_enable_serial_irqs() argument
78 dm_pci_write_config8(pch, SERIRQ_CNTL, value); in pch_enable_serial_irqs()
80 dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6)); in pch_enable_serial_irqs()
84 static int pch_pirq_init(struct udevice *pch) in pch_pirq_init() argument
88 if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch), in pch_pirq_init()
92 dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++); in pch_pirq_init()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/soc/
H A Dintel_pch.c10 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
16 drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n"); in intel_pch_type()
20 drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n"); in intel_pch_type()
25 drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n"); in intel_pch_type()
31 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n"); in intel_pch_type()
38 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint LP PCH\n"); in intel_pch_type()
45 drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint PCH\n"); in intel_pch_type()
53 drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint LP PCH\n"); in intel_pch_type()
61 drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint PCH\n"); in intel_pch_type()
66 drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n"); in intel_pch_type()
[all …]
H A Dintel_pch.h13 * If the new PCH comes with a south display engine that is not
15 * end. Instead, add it right after its "parent" PCH.
18 PCH_NOP = -1, /* PCH without south display */
19 PCH_NONE = 0, /* No PCH present */
20 PCH_IBX, /* Ibexpeak PCH */
21 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
22 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
23 PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
24 PCH_CNP, /* Cannon/Comet Lake PCH */
25 PCH_ICP, /* Ice Lake/Jasper Lake PCH */
[all …]
/openbmc/linux/drivers/net/ppp/
H A Dppp_generic.c264 static void ppp_channel_push(struct channel *pch);
266 struct channel *pch);
273 struct channel *pch);
288 static int ppp_connect_channel(struct channel *pch, int unit);
289 static int ppp_disconnect_channel(struct channel *pch);
290 static void ppp_destroy_channel(struct channel *pch);
639 static int ppp_bridge_channels(struct channel *pch, struct channel *pchb) in ppp_bridge_channels() argument
641 write_lock_bh(&pch->upl); in ppp_bridge_channels()
642 if (pch->ppp || in ppp_bridge_channels()
643 rcu_dereference_protected(pch->bridge, lockdep_is_held(&pch->upl))) { in ppp_bridge_channels()
[all …]
/openbmc/linux/drivers/dma/
H A Dpl330.c1559 struct dma_pl330_chan *pch; in dma_pl330_rqcb() local
1565 pch = desc->pchan; in dma_pl330_rqcb()
1568 if (!pch) in dma_pl330_rqcb()
1571 spin_lock_irqsave(&pch->lock, flags); in dma_pl330_rqcb()
1575 spin_unlock_irqrestore(&pch->lock, flags); in dma_pl330_rqcb()
1577 tasklet_schedule(&pch->task); in dma_pl330_rqcb()
2042 static inline void fill_queue(struct dma_pl330_chan *pch) in fill_queue() argument
2047 list_for_each_entry(desc, &pch->work_list, node) { in fill_queue()
2053 ret = pl330_submit_req(pch->thread, desc); in fill_queue()
2062 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", in fill_queue()
[all …]
/openbmc/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
43 | PCH-PIC | | PCH-MSI |
48 | PCH-LPC | | Devices | | Devices |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
75 | PCH-PIC | | PCH-MSI |
80 | PCH-LPC | | Devices | | Devices |
115 PCH-PIC::
[all …]
/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
46 | PCH-PIC | | PCH-MSI |
51 | PCH-LPC | | Devices | | Devices |
64 PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
77 | PCH-PIC | | PCH-MSI |
82 | PCH-LPC | | Devices | | Devices |
117 PCH-PIC::
[all …]
/openbmc/linux/Documentation/i2c/busses/
H A Di2c-i801.rst21 * Intel 5/3400 Series (PCH)
22 * Intel 6 Series (PCH)
23 * Intel Patsburg (PCH)
24 * Intel DH89xxCC (PCH)
25 * Intel Panther Point (PCH)
26 * Intel Lynx Point (PCH)
28 * Intel Wellsburg (PCH)
29 * Intel Coleto Creek (PCH)
30 * Intel Wildcat Point (PCH)
33 * Intel Sunrise Point (PCH)
[all …]
/openbmc/linux/drivers/pinctrl/intel/
H A DKconfig28 Lynxpoint is the PCH of Intel Haswell. This pinctrl driver
29 provides an interface that allows configuring of PCH pins and
45 of Intel Alder Lake PCH pins and using them as GPIOs.
55 tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
59 of Intel Cannon Lake PCH pins and using them as GPIOs.
66 of Intel Cedar Fork PCH pins and using them as GPIOs.
97 tristate "Intel Ice Lake PCH pinctrl and GPIO driver"
101 of Intel Ice Lake PCH pins and using them as GPIOs.
104 tristate "Intel Jasper Lake PCH pinctrl and GPIO driver"
108 of Intel Jasper Lake PCH pins and using them as GPIOs.
[all …]
/openbmc/u-boot/arch/x86/cpu/intel_common/
H A Dlpc.c10 #include <pch.h>
19 static void enable_spi_prefetch(struct udevice *pch) in enable_spi_prefetch() argument
23 dm_pci_read_config8(pch, 0xdc, &reg8); in enable_spi_prefetch()
26 dm_pci_write_config8(pch, 0xdc, reg8); in enable_spi_prefetch()
29 static void enable_port80_on_lpc(struct udevice *pch) in enable_port80_on_lpc() argument
32 dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1); in enable_port80_on_lpc()
44 struct udevice *pch = dev->parent; in lpc_common_early_init() local
59 dm_pci_write_config16(pch, LPC_IO_DEC, 0x0010); in lpc_common_early_init()
62 dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | MC_LPC_EN | in lpc_common_early_init()
72 dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg); in lpc_common_early_init()
[all …]
/openbmc/linux/drivers/thermal/intel/
H A Dintel_pch_thermal.c2 /* intel_pch_thermal.c - Intel PCH Thermal driver
21 /* Intel PCH thermal Device IDs */
22 #define PCH_THERMAL_DID_HSW_1 0x9C24 /* Haswell PCH */
23 #define PCH_THERMAL_DID_HSW_2 0x8C24 /* Haswell PCH */
25 #define PCH_THERMAL_DID_SKL 0x9D31 /* Skylake PCH */
26 #define PCH_THERMAL_DID_SKL_H 0xA131 /* Skylake PCH 100 series */
27 #define PCH_THERMAL_DID_CNL 0x9Df9 /* CNL PCH */
28 #define PCH_THERMAL_DID_CNL_H 0xA379 /* CNL-H PCH */
29 #define PCH_THERMAL_DID_CNL_LP 0x02F9 /* CNL-LP PCH */
30 #define PCH_THERMAL_DID_CML_H 0X06F9 /* CML-H PCH */
[all …]
/openbmc/u-boot/include/
H A Dpch.h14 /* All the supported PCH ioctls */
35 * @dev: PCH device to check
44 * @dev: PCH device to adjust
54 * @dev: PCH device to check
63 * @dev: PCH device to check
77 * @dev: PCH device to check
78 * @req: PCH request ID
92 * @dev: PCH device to check
101 * @dev: PCH device to adjust
111 * @dev: PCH device to check
[all …]
/openbmc/u-boot/board/intel/cougarcanyon2/
H A Dcougarcanyon2.c14 #include <asm/arch/pch.h>
20 struct udevice *pch; in board_early_init_f() local
23 ret = uclass_first_device(UCLASS_PCH, &pch); in board_early_init_f()
26 if (!pch) in board_early_init_f()
30 dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE); in board_early_init_f()
31 dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | COMA_LPC_EN); in board_early_init_f()
32 dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B | in board_early_init_f()
34 dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B | in board_early_init_f()
/openbmc/openbmc/meta-ibm/meta-system1/recipes-phosphor/flash/phosphor-software-manager/
H A Dbios-update.sh5 # Check if PCH is on standby to proceed with the
8 # Find the GPIO pin associated with "pch-ready"
10 PCH_READY_GPIO_PIN=$(gpiofind "pch-ready")
13 echo "gpio 'pch-ready' not found in device tree. Exiting."
21 echo "PCH is not on standby. Exiting host firmware version read."
72 # 1. Assert PCH RESET
74 # 3. De-assert PCH RESET
77 echo "Asserting PCH RESET and enabling flash write override"
83 echo "Disabling flash write override and resetting PCH RESET"
106 PCH_RESET_GPIO_PIN=$(gpiofind "pch-reset")
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_fifo_underrun.c55 * The code also supports underrun detection on the PCH transcoder.
251 drm_err(&dev_priv->drm, "pch fifo underrun on pch transcoder %c\n", in cpt_check_pch_fifo_underruns()
275 "uncleared pch fifo underrun on pch transcoder %c\n", in cpt_set_fifo_underrun_reporting()
336 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
338 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
341 * This function makes us disable or enable PCH fifo underruns for a specific
342 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
343 * underrun reporting for one transcoder may also disable all the other PCH
359 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT in intel_set_pch_fifo_underrun_reporting()
360 * has only one pch transcoder A that all pipes can use. To avoid racy in intel_set_pch_fifo_underrun_reporting()
[all …]
H A Dintel_pch_display.c47 "PCH DP %c enabled on transcoder %c, should be disabled\n", in assert_pch_dp_disabled()
52 "IBX PCH DP %c still using transcoder B\n", in assert_pch_dp_disabled()
66 "PCH HDMI %c enabled on transcoder %c, should be disabled\n", in assert_pch_hdmi_disabled()
71 "IBX PCH HDMI %c still using transcoder B\n", in assert_pch_hdmi_disabled()
86 "PCH VGA enabled on transcoder %c, should be disabled\n", in assert_pch_ports_disabled()
91 "PCH LVDS enabled on transcoder %c, should be disabled\n", in assert_pch_ports_disabled()
94 /* PCH SDVOB multiplex with HDMIB */ in assert_pch_ports_disabled()
154 * The BIOS may select transcoder B on some of the PCH in ibx_sanitize_pch_ports()
168 /* PCH SDVOB multiplex with HDMIB */ in ibx_sanitize_pch_ports()
250 /* Make sure PCH DPLL is enabled */ in ilk_enable_pch_transcoder()
[all …]
/openbmc/openbmc/meta-ibm/meta-system1/recipes-phosphor/flash/
H A Dbios-version.bb16 file://pch-standby.service \
17 file://pch-standby-check.sh \
23 install -m 0755 ${UNPACKDIR}/pch-standby-check.sh ${D}${libexecdir}/
27 install -m 0644 ${UNPACKDIR}/pch-standby.service ${D}${systemd_system_unitdir}/
31 SYSTEMD_SERVICE:${PN} += "pch-standby.service"
34 FILES:${PN} += "${systemd_system_unitdir}/pch-standby.service ${libexecdir}/pch-standby-check.sh"
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,pch-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
7 title: Loongson PCH MSI Controller
13 This interrupt controller is found in the Loongson LS7A family of PCH for
19 const: loongson,pch-msi-1.0
27 to PCH MSI.
35 to PCH MSI.
55 compatible = "loongson,pch-msi-1.0";
H A Dloongson,pch-pic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
7 title: Loongson PCH PIC Controller
13 This interrupt controller is found in the Loongson LS7A family of PCH for
19 const: loongson,pch-pic-1.0
27 to PCH PIC.
50 compatible = "loongson,pch-pic-1.0";
/openbmc/openbmc/poky/meta/recipes-devtools/patch/patch/
H A DCVE-2019-20633.patch6 * src/pch.c (another_hunk): Avoid invalid memory access in context format
14 src/pch.c | 1 +
17 diff --git a/src/pch.c b/src/pch.c
19 --- a/src/pch.c
20 +++ b/src/pch.c
H A D0002-Fix-segfault-with-mangled-rename-patch.patch7 * src/pch.c (intuit_diff_type): Ensure that two filenames are specified
16 src/pch.c | 3 ++-
19 diff --git a/src/pch.c b/src/pch.c
21 --- a/src/pch.c
22 +++ b/src/pch.c
H A D0001-Fix-swapping-fake-lines-in-pch_swap.patch6 * src/pch.c (pch_swap): Fix swapping p_bfake and p_efake when there is a
18 src/pch.c | 2 +-
21 diff --git a/src/pch.c b/src/pch.c
23 --- a/src/pch.c
24 +++ b/src/pch.c
H A D0003-Allow-input-files-to-be-missing-for-ed-style-patches.patch6 * src/pch.c (do_ed_script): Allow input files to be missing so that new
14 src/pch.c | 8 +++++---
17 diff --git a/src/pch.c b/src/pch.c
19 --- a/src/pch.c
20 +++ b/src/pch.c
/openbmc/linux/tools/bpf/bpftool/
H A Dperf.c159 const char *pch; in show_proc() local
168 pch = proc_de->d_name; in show_proc()
171 while (isdigit(*pch)) { in show_proc()
172 pid = pid * 10 + *pch - '0'; in show_proc()
173 pch++; in show_proc()
175 if (*pch != '\0') in show_proc()
188 pch = pid_fd_de->d_name; in show_proc()
191 while (isdigit(*pch)) { in show_proc()
192 fd = fd * 10 + *pch - '0'; in show_proc()
193 pch++; in show_proc()
[all …]
/openbmc/openbmc/meta-ibm/meta-system1/recipes-phosphor/flash/bios-version/
H A Dpch-standby-check.sh3 # Find the GPIO pin associated with "pch-ready"
4 GPIO_PIN=$(gpiofind "pch-ready")
7 echo "gpio 'pch-ready' not found in device tree. Exiting."
20 echo "PCH Standby Power Sequence Complete"
23 echo "Waiting for PCH Standby Power Sequence..."

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