Lines Matching full:pch
20 #include <asm/arch/pch.h>
29 static int pch_enable_apic(struct udevice *pch) in pch_enable_apic() argument
35 dm_pci_write_config8(pch, ACPI_CNTL, 0x80); in pch_enable_apic()
48 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); in pch_enable_apic()
71 static void pch_enable_serial_irqs(struct udevice *pch) in pch_enable_serial_irqs() argument
78 dm_pci_write_config8(pch, SERIRQ_CNTL, value); in pch_enable_serial_irqs()
80 dm_pci_write_config8(pch, SERIRQ_CNTL, value | (1 << 6)); in pch_enable_serial_irqs()
84 static int pch_pirq_init(struct udevice *pch) in pch_pirq_init() argument
88 if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch), in pch_pirq_init()
92 dm_pci_write_config8(pch, PIRQA_ROUT, *ptr++); in pch_pirq_init()
93 dm_pci_write_config8(pch, PIRQB_ROUT, *ptr++); in pch_pirq_init()
94 dm_pci_write_config8(pch, PIRQC_ROUT, *ptr++); in pch_pirq_init()
95 dm_pci_write_config8(pch, PIRQD_ROUT, *ptr++); in pch_pirq_init()
97 dm_pci_write_config8(pch, PIRQE_ROUT, *ptr++); in pch_pirq_init()
98 dm_pci_write_config8(pch, PIRQF_ROUT, *ptr++); in pch_pirq_init()
99 dm_pci_write_config8(pch, PIRQG_ROUT, *ptr++); in pch_pirq_init()
100 dm_pci_write_config8(pch, PIRQH_ROUT, *ptr++); in pch_pirq_init()
109 static int pch_gpi_routing(struct udevice *pch) in pch_gpi_routing() argument
115 if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch), in pch_gpi_routing()
122 dm_pci_write_config32(pch, 0xb8, reg); in pch_gpi_routing()
127 static int pch_power_options(struct udevice *pch) in pch_power_options() argument
130 int node = dev_of_offset(pch); in pch_power_options()
149 dm_pci_read_config16(pch, GEN_PMCON_3, ®16); in pch_power_options()
176 dm_pci_write_config16(pch, GEN_PMCON_3, reg16); in pch_power_options()
200 dm_pci_read_config16(pch, GEN_PMCON_1, ®16); in pch_power_options()
204 /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */ in pch_power_options()
207 dm_pci_write_config16(pch, GEN_PMCON_1, reg16); in pch_power_options()
210 ret = pch_gpi_routing(pch); in pch_power_options()
214 dm_pci_read_config16(pch, 0x40, &pmbase); in pch_power_options()
235 static void pch_rtc_init(struct udevice *pch) in pch_rtc_init() argument
240 dm_pci_read_config8(pch, GEN_PMCON_3, ®8); in pch_rtc_init()
244 dm_pci_write_config8(pch, GEN_PMCON_3, reg8); in pch_rtc_init()
253 /* CougarPoint PCH Power Management init */
254 static void cpt_pm_init(struct udevice *pch) in cpt_pm_init() argument
257 dm_pci_write_config8(pch, 0xa9, 0x47); in cpt_pm_init()
297 /* PantherPoint PCH Power Management init */
298 static void ppt_pm_init(struct udevice *pch) in ppt_pm_init() argument
301 dm_pci_write_config8(pch, 0xa9, 0x47); in ppt_pm_init()
348 static void enable_clock_gating(struct udevice *pch) in enable_clock_gating() argument
355 dm_pci_read_config16(pch, GEN_PMCON_1, ®16); in enable_clock_gating()
357 dm_pci_write_config16(pch, GEN_PMCON_1, reg16); in enable_clock_gating()
359 pch_iobp_update(pch, 0xeb007f07, ~0U, 1 << 31); in enable_clock_gating()
360 pch_iobp_update(pch, 0xeb004000, ~0U, 1 << 7); in enable_clock_gating()
361 pch_iobp_update(pch, 0xec007f07, ~0U, 1 << 31); in enable_clock_gating()
362 pch_iobp_update(pch, 0xec004000, ~0U, 1 << 7); in enable_clock_gating()
384 static void pch_disable_smm_only_flashing(struct udevice *pch) in pch_disable_smm_only_flashing() argument
389 dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */ in pch_disable_smm_only_flashing()
391 dm_pci_write_config8(pch, 0xdc, reg8); in pch_disable_smm_only_flashing()
394 static void pch_fixups(struct udevice *pch) in pch_fixups() argument
399 dm_pci_read_config8(pch, GEN_PMCON_2, &gen_pmcon_2); in pch_fixups()
401 dm_pci_write_config8(pch, GEN_PMCON_2, gen_pmcon_2); in pch_fixups()
403 /* Enable DMI ASPM in the PCH */ in pch_fixups()
427 struct udevice *pch = dev->parent; in lpc_init_extra() local
429 debug("pch: lpc_init\n"); in lpc_init_extra()
430 dm_pci_write_bar32(pch, 0, 0); in lpc_init_extra()
431 dm_pci_write_bar32(pch, 1, 0xff800000); in lpc_init_extra()
432 dm_pci_write_bar32(pch, 2, 0xfec00000); in lpc_init_extra()
433 dm_pci_write_bar32(pch, 3, 0x800); in lpc_init_extra()
434 dm_pci_write_bar32(pch, 4, 0x900); in lpc_init_extra()
437 dm_pci_write_config16(pch, PCI_COMMAND, 0x000f); in lpc_init_extra()
440 pch_enable_apic(pch); in lpc_init_extra()
442 pch_enable_serial_irqs(pch); in lpc_init_extra()
445 pch_pirq_init(pch); in lpc_init_extra()
448 pch_power_options(pch); in lpc_init_extra()
451 switch (pch_silicon_type(pch)) { in lpc_init_extra()
453 cpt_pm_init(pch); in lpc_init_extra()
456 ppt_pm_init(pch); in lpc_init_extra()
459 printf("Unknown Chipset: %s\n", pch->name); in lpc_init_extra()
464 pch_rtc_init(pch); in lpc_init_extra()
470 enable_clock_gating(pch); in lpc_init_extra()
472 pch_disable_smm_only_flashing(pch); in lpc_init_extra()
474 pch_fixups(pch); in lpc_init_extra()