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/openbmc/u-boot/arch/arm/mach-stm32mp/
H A Dbsec.c25 #define BSEC_SWLOCK_OFF 0x07C /* write in OTP sticky lock */
47 * OTP Lock services definition
53 * bsec_check_error() - Check status of one otp
55 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
58 static u32 bsec_check_error(u32 base, u32 otp) in bsec_check_error() argument
63 bit = 1 << (otp & OTP_LOCK_MASK); in bsec_check_error()
64 bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32); in bsec_check_error()
77 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
80 static bool bsec_read_lock(u32 address, u32 otp) in bsec_read_lock() argument
85 bit = 1 << (otp & OTP_LOCK_MASK); in bsec_read_lock()
[all …]
H A Dcpu.c57 /* BSEC OTP index */
286 * (silently) from the value in the OTP.
293 u32 otp[2]; in setup_mac_address() local
308 otp, sizeof(otp)); in setup_mac_address()
313 enetaddr[i] = ((uint8_t *)&otp)[i]; in setup_mac_address()
316 pr_err("invalid MAC address in OTP %pM", enetaddr); in setup_mac_address()
319 pr_debug("OTP MAC address = %pM\n", enetaddr); in setup_mac_address()
322 pr_err("Failed to set mac address %pM from OTP: %d\n", in setup_mac_address()
332 u32 otp[3] = {0, 0, 0 }; in setup_serial_number() local
346 otp, sizeof(otp)); in setup_serial_number()
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/openbmc/linux/drivers/nvmem/
H A Drockchip-otp.c3 * Rockchip OTP Driver
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
85 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
89 ret = reset_control_assert(otp->rst); in rockchip_otp_reset()
91 dev_err(otp->dev, "failed to assert otp phy %d\n", ret); in rockchip_otp_reset()
97 ret = reset_control_deassert(otp->rst); in rockchip_otp_reset()
99 dev_err(otp->dev, "failed to deassert otp phy %d\n", ret); in rockchip_otp_reset()
106 static int rockchip_otp_wait_status(struct rockchip_otp *otp, in rockchip_otp_wait_status() argument
112 ret = readl_poll_timeout_atomic(otp->base + reg, status, in rockchip_otp_wait_status()
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H A Dlan9662-otpc.c47 static int lan9662_otp_power(struct lan9662_otp *otp, bool up) in lan9662_otp_power() argument
49 void __iomem *pwrdn = OTP_OTP_PWR_DN(otp->base); in lan9662_otp_power()
53 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_power()
63 static int lan9662_otp_execute(struct lan9662_otp *otp) in lan9662_otp_execute() argument
65 if (lan9662_otp_wait_flag_clear(OTP_OTP_CMD_GO(otp->base), in lan9662_otp_execute()
69 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_execute()
76 static void lan9662_otp_set_address(struct lan9662_otp *otp, u32 offset) in lan9662_otp_set_address() argument
78 writel(0xff & (offset >> 8), OTP_OTP_ADDR_HI(otp->base)); in lan9662_otp_set_address()
79 writel(0xff & offset, OTP_OTP_ADDR_LO(otp->base)); in lan9662_otp_set_address()
82 static int lan9662_otp_read_byte(struct lan9662_otp *otp, u32 offset, u8 *dst) in lan9662_otp_read_byte() argument
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H A Dsunplus-ocotp.c21 * OTP memory
78 static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value) in sp_otp_read_real() argument
94 writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK & in sp_otp_read_real()
95 OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS); in sp_otp_read_real()
96 writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS); in sp_otp_read_real()
97 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ, in sp_otp_read_real()
98 otp->base[OTPRX] + OTP_CONTROL_2); in sp_otp_read_real()
99 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) & SEL_BAK_KEY2_MASK & SW_TRIM_EN_MASK in sp_otp_read_real()
101 otp->base[OTPRX] + OTP_CONTROL_2); in sp_otp_read_real()
102 writel((readl(otp->base[OTPRX] + OTP_CONTROL_2) & OTP_RD_PERIOD_MASK) | CPU_CLOCK, in sp_otp_read_real()
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H A Dmxs-ocotp.c3 * Freescale MXS On-Chip OTP driver
36 static int mxs_ocotp_wait(struct mxs_ocotp *otp) in mxs_ocotp_wait() argument
42 status = readl(otp->base); in mxs_ocotp_wait()
61 struct mxs_ocotp *otp = context; in mxs_ocotp_read() local
65 ret = clk_enable(otp->clk); in mxs_ocotp_read()
69 writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR); in mxs_ocotp_read()
71 ret = mxs_ocotp_wait(otp); in mxs_ocotp_read()
76 writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET); in mxs_ocotp_read()
81 ret = mxs_ocotp_wait(otp); in mxs_ocotp_read()
90 *buf++ = readl(otp->base + offset); in mxs_ocotp_read()
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H A Dlpc18xx_otp.c3 * NXP LPC18xx/43xx OTP memory NVMEM driver
10 * TODO: add support for writing OTP register via API in boot ROM.
21 * LPC18xx OTP memory contains 4 banks with 4 32-bit words. Bank 0 starts
43 struct lpc18xx_otp *otp = context; in lpc18xx_otp_read() local
53 *buf++ = readl(otp->base + i * LPC18XX_OTP_WORD_SIZE); in lpc18xx_otp_read()
59 .name = "lpc18xx-otp",
69 struct lpc18xx_otp *otp; in lpc18xx_otp_probe() local
71 otp = devm_kzalloc(&pdev->dev, sizeof(*otp), GFP_KERNEL); in lpc18xx_otp_probe()
72 if (!otp) in lpc18xx_otp_probe()
75 otp->base = devm_platform_ioremap_resource(pdev, 0); in lpc18xx_otp_probe()
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H A DKconfig43 tristate "Broadcom On-Chip OTP Controller support"
48 Say y here to enable read/write access to the Broadcom OTP
75 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
79 This is a driver for the On-Chip OTP Controller (OCOTP) available on
87 tristate "i.MX On-Chip OTP Controller support"
92 This is a driver for the On-Chip OTP Controller (OCOTP)
96 tristate "i.MX8 SCU On-Chip OTP Controller support"
100 This is a driver for the SCU On-Chip OTP Controller (OCOTP)
116 tristate "Microchip LAN9662 OTP controller support"
120 This driver enables the OTP controller available on Microchip LAN9662
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H A Dnintendo-otp.c3 * Nintendo Wii and Wii U OTP driver
5 * This is a driver exposing the OTP of a Nintendo Wii or Wii U console.
10 * Based on reversed documentation from https://wiiubrew.org/wiki/Hardware/OTP
39 .name = "wii-otp",
44 .name = "wiiu-otp",
68 { .compatible = "nintendo,hollywood-otp", .data = &hollywood_otp_data },
69 { .compatible = "nintendo,latte-otp", .data = &latte_otp_data },
115 .name = "nintendo-otp",
121 MODULE_DESCRIPTION("Nintendo Wii and Wii U OTP driver");
/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Drockchip,otp.yaml4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3588-otp
29 - const: otp
58 - rockchip,px30-otp
59 - rockchip,rk3308-otp
75 - rockchip,rk3588-otp
84 - const: otp
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H A Dnintendo-otp.yaml4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
14 See https://wiiubrew.org/wiki/Hardware/OTP
25 - nintendo,hollywood-otp
26 - nintendo,latte-otp
39 otp@d8001ec {
40 compatible = "nintendo,latte-otp";
H A Dlpc1850-otp.txt1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
H A Dbrcm,ocotp.txt1 Broadcom OTP memory controller
8 - reg: Base address of the OTP controller.
13 otp: otp@301c800 {
H A Dst,stm32-romem.yaml11 flash, OTP, read-only HW regs... This contains various information such as:
24 - st,stm32f4-otp
36 st,non-secure-otp:
54 compatible = "st,stm32f4-otp";
65 st,non-secure-otp;
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-eeprom-read.c85 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp); in iwl_eeprom_verify_signature()
92 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n", in iwl_eeprom_verify_signature()
93 nvm_is_otp ? "OTP" : "EEPROM", gp); in iwl_eeprom_verify_signature()
100 * OTP related functions
116 /* OTP only valid for CP/PP and after */ in iwl_nvm_is_otp()
150 * this is only applicable for HW with OTP shadow RAM in iwl_init_otp_access()
173 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr); in iwl_read_otp_word()
181 /* set the uncorrectable OTP ECC bit for acknowledgment */ in iwl_read_otp_word()
184 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n"); in iwl_read_otp_word()
189 /* set the correctable OTP ECC bit for acknowledgment */ in iwl_read_otp_word()
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/openbmc/linux/drivers/mtd/spi-nor/
H A Dotp.c3 * OTP support for SPI NOR flashes
14 #define spi_nor_otp_region_len(nor) ((nor)->params->otp.org->len)
15 #define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org->n_regions)
28 * 256). Thus one "security register" maps to one OTP region.
166 * spi_nor_otp_lock_sr2() - lock the OTP region
168 * @region: OTP region
170 * Lock the OTP region by writing the status register-2. This method is used on
198 * spi_nor_otp_is_locked_sr2() - get the OTP region lock status
200 * @region: OTP region
202 * Retrieve the OTP region lock bit by reading the status register-2. This
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Deeprom.c57 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7615_efuse_init()
58 dev->mt76.otp.size = len; in mt7615_efuse_init()
59 if (!dev->mt76.otp.data) in mt7615_efuse_init()
62 buf = dev->mt76.otp.data; in mt7615_efuse_init()
278 u8 *otp = dev->mt76.otp.data; in mt7615_apply_cal_free_data() local
281 if (!otp) in mt7615_apply_cal_free_data()
285 if (!otp[ical[i]]) in mt7615_apply_cal_free_data()
289 eeprom[ical[i]] = otp[ical[i]]; in mt7615_apply_cal_free_data()
292 eeprom[ical_nocheck[i]] = otp[ical_nocheck[i]]; in mt7615_apply_cal_free_data()
301 u8 *otp = dev->mt76.otp.data; in mt7622_apply_cal_free_data() local
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/openbmc/openbmc/meta-aspeed/classes/
H A Dotptool.bbclass2 # to create OTP image
26 bbfatal "Generated OTP image failed."
29 otptool print "${otptool_config_outdir}"/otp-all.image
32 bbfatal "Printed OTP image failed."
36 "${otptool_config_outdir}"/otp-all.image \
37 ${DEPLOYDIR}/"${otptool_config_slug}"-otp-all.image
40 # Creates the OTP image
43 bbwarn "OTP creation is only supported on AST2600 boards"
/openbmc/qemu/include/hw/nvram/
H A Dbcm2835_otp.h2 * BCM2835 One-Time Programmable (OTP) Memory
15 #define TYPE_BCM2835_OTP "bcm2835-otp"
20 /* https://elinux.org/BCM2835_registers#OTP */
37 /* Lock OTP Programming (Customer OTP and private key) */
40 /* -- Row 36-43: Customer OTP -- */
45 /* Magic numbers to lock programming of customer OTP and private key */
H A Dnpcm7xx_otp.h2 * Nuvoton NPCM7xx OTP (Fuse Array) Interface
22 /* Each OTP module holds 8192 bits of one-time programmable storage */
44 * struct NPCM7xxOTPState - Device state for one OTP module.
48 * @array: OTP storage array.
58 #define TYPE_NPCM7XX_OTP "npcm7xx-otp"
67 * npcm7xx_otp_array_write - ECC encode and write data to OTP array.
68 * @s: OTP module.
70 * @offset: Offset of first byte to be written in the OTP array.
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dmtd.yaml45 "^otp(-[0-9]+)?$":
50 An OTP memory region. Some flashes provide a one-time-programmable
57 - user-otp
58 - factory-otp
88 otp-1 {
89 compatible = "factory-otp";
98 otp-2 {
99 compatible = "user-otp";
/openbmc/qemu/hw/nvram/
H A Dnpcm7xx_otp.c2 * Nuvoton NPCM7xx OTP (Fuse Array) Interface
62 * struct NPCM7xxOTPClass - OTP module class.
66 * The two OTP modules (key-storage and fuse-array) have slightly different
106 /* Common register read handler for both OTP classes. */
134 /* Read a byte from the OTP array into the data register. */
143 /* Program a byte from the data register into the OTP array. */
175 /* Common register write handler for both OTP classes. */
253 /* Register read handler specific to the fuse array OTP module. */
263 * work the same way for both kinds of OTP modules. in npcm7xx_fuse_array_read()
268 /* FUSTRAP is stored as three copies in the OTP array. */ in npcm7xx_fuse_array_read()
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Deeprom.c51 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7603_efuse_init()
52 dev->mt76.otp.size = len; in mt7603_efuse_init()
53 if (!dev->mt76.otp.data) in mt7603_efuse_init()
56 buf = dev->mt76.otp.data; in mt7603_efuse_init()
109 if (!np || !of_property_read_bool(np, "mediatek,eeprom-merge-otp")) in mt7603_apply_cal_free_data()
165 if (dev->mt76.otp.data) { in mt7603_eeprom_init()
167 mt7603_apply_cal_free_data(dev, dev->mt76.otp.data); in mt7603_eeprom_init()
169 memcpy(dev->mt76.eeprom.data, dev->mt76.otp.data, in mt7603_eeprom_init()
/openbmc/linux/include/linux/mfd/wm831x/
H A Dotp.h3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
73 * R30728 (0x7808) - Factory OTP ID
84 * R30729 (0x7809) - Factory OTP 1
97 * R30730 (0x780A) - Factory OTP 2
104 * R30731 (0x780B) - Factory OTP 3
117 * R30732 (0x780C) - Factory OTP 4
128 * R30733 (0x780D) - Factory OTP 5
135 * R30736 (0x7810) - Customer OTP ID
/openbmc/u-boot/board/imgtec/ci20/
H A Dci20.c167 struct ci20_otp otp; in misc_init_r() local
170 /* Read the board OTP data */ in misc_init_r()
172 jz4780_efuse_read(0x18, 16, (u8 *)&otp); in misc_init_r()
175 if (!is_valid_ethaddr(otp.mac)) { in misc_init_r()
177 jz4780_efuse_read(0x8, 4, &otp.mac[0]); in misc_init_r()
178 jz4780_efuse_read(0x12, 2, &otp.mac[4]); in misc_init_r()
179 otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01; in misc_init_r()
181 eth_env_set_enetaddr("ethaddr", otp.mac); in misc_init_r()
184 env_set_ulong("serial#", otp.serial_number); in misc_init_r()
185 env_set_ulong("board_date", otp.date); in misc_init_r()
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