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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5433-clock.yaml18 - "oscclk" - PLL input clock from XXTI
106 - const: oscclk
126 - const: oscclk
143 - const: oscclk
161 - const: oscclk
187 - const: oscclk
206 - const: oscclk
231 - const: oscclk
283 - const: oscclk
301 - const: oscclk
[all …]
H A Dsamsung,exynos850-clock.yaml20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
75 - const: oscclk
92 - const: oscclk
110 - const: oscclk
128 - const: oscclk
149 - const: oscclk
170 - const: oscclk
188 - const: oscclk
209 - const: oscclk
233 - const: oscclk
[all …]
H A Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
21 The external OSCCLK must be defined as fixed-rate clock in dts.
74 - const: oscclk
91 - const: oscclk
109 - const: oscclk
128 - const: oscclk
149 - const: oscclk
171 - const: oscclk
192 - const: oscclk
212 - const: oscclk
[all …]
H A Dsamsung,exynos7885-clock.yaml20 is an external clock: OSCCLK (26 MHz). This external clock must be defined
68 - const: oscclk
87 - const: oscclk
111 - const: oscclk
141 - const: oscclk
171 clocks = <&oscclk>,
181 clock-names = "oscclk",
H A Dsamsung,exynos-ext-clock.yaml23 - samsung,exynos5420-oscclk
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos850.dtsi49 oscclk: clock-oscclk { label
51 clock-output-names = "oscclk";
183 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
217 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
228 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
240 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
243 clock-names = "oscclk", "dout_peri_bus",
252 clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
253 clock-names = "oscclk", "dout_g3d_switch";
261 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
[all …]
H A Dexynos7885.dtsi161 oscclk: osc-clock { label
164 clock-output-names = "oscclk";
197 clocks = <&oscclk>,
207 clock-names = "oscclk",
224 clocks = <&oscclk>,
228 clock-names = "oscclk",
239 clocks = <&oscclk>;
240 clock-names = "oscclk";
248 clocks = <&oscclk>,
254 clock-names = "oscclk",
H A Dexynos5433.dtsi47 clock-output-names = "oscclk";
373 clock-names = "oscclk",
388 clock-names = "oscclk";
397 clock-names = "oscclk",
420 clock-names = "oscclk",
447 clock-names = "oscclk",
461 clock-names = "oscclk",
486 clock-names = "oscclk", "fout_aud_pll";
514 clock-names = "oscclk", "aclk_bus2_400";
523 clock-names = "oscclk", "aclk_g3d_400";
[all …]
H A Dexynos850-e850-96.dts129 clocks = <&oscclk>, <&rtcclk>,
133 clock-names = "oscclk", "rtcclk", "dout_hsi_bus",
157 &oscclk {
H A Dexynosautov9.dtsi158 clock-output-names = "oscclk";
180 clock-names = "oscclk",
192 clock-names = "oscclk",
205 clock-names = "oscclk",
219 clock-names = "oscclk",
233 clock-names = "oscclk",
247 clock-names = "oscclk",
260 clock-names = "oscclk",
271 clock-names = "oscclk",
281 clock-names = "oscclk";
H A Dexynos7885-jackpotlte.dts84 &oscclk {
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos7885.c157 PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
160 PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
175 PNAME(mout_peri_spi0_p) = { "oscclk", "dout_shared0_div4" };
176 PNAME(mout_peri_spi1_p) = { "oscclk", "dout_shared0_div4" };
177 PNAME(mout_peri_uart0_p) = { "oscclk", "dout_shared0_div4" };
178 PNAME(mout_peri_uart1_p) = { "oscclk", "dout_shared0_div4" };
179 PNAME(mout_peri_uart2_p) = { "oscclk", "dout_shared0_div4" };
180 PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" };
181 PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" };
182 PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" };
[all …]
H A Dclk-exynos850.c207 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
210 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
213 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
218 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
219 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
220 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
231 PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
234 "oscclk", "oscclk" };
242 PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
245 "oscclk", "oscclk" };
[all …]
H A Dclk-exynos5433.c213 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
214 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
215 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
216 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
217 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
218 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
219 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
220 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
251 "oscclk", "ioclk_spdif_extclk", };
252 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
[all …]
H A Dclk-exynosautov9.c353 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
355 PLL(pll_0822x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
357 PLL(pll_0822x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
359 PLL(pll_0822x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
361 PLL(pll_0822x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
366 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
367 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
368 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
369 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
370 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
[all …]
/openbmc/qemu/include/hw/misc/
H A Dmps2-scc.h22 * + QOM property array "oscclk": reset values of the OSCCLK registers
63 uint32_t *oscclk; member
/openbmc/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos-hdmi.yaml121 - description: MUX used to switch between oscclk and tmds_clko,
124 - description: MUX used to switch between oscclk and pixel_clko,
139 - const: oscclk
195 "oscclk",
/openbmc/qemu/hw/misc/
H A Dmps2-scc.c123 s->oscclk[device] = value; in scc_cfg_write()
141 *value = s->oscclk[device]; in scc_cfg_read()
377 s->oscclk[i] = s->oscclk_reset[i]; in mps2_scc_reset()
405 s->oscclk = g_new0(uint32_t, s->num_oscclk); in mps2_scc_realize()
449 VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
473 DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset,
/openbmc/qemu/hw/arm/
H A Dmps2.c142 QList *oscclk; in mps2_common_init() local
400 /* All these FPGA images have the same OSCCLK configuration */ in mps2_common_init()
401 oscclk = qlist_new(); in mps2_common_init()
402 qlist_append_int(oscclk, 50000000); in mps2_common_init()
403 qlist_append_int(oscclk, 24576000); in mps2_common_init()
404 qlist_append_int(oscclk, 25000000); in mps2_common_init()
405 qdev_prop_set_array(sccdev, "oscclk", oscclk); in mps2_common_init()
H A Dmps3r.c360 QList *oscclk; in mps3r_common_init() local
520 oscclk = qlist_new(); in mps3r_common_init()
522 qlist_append_int(oscclk, an536_oscclk[i]); in mps3r_common_init()
524 qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk); in mps3r_common_init()
H A Dmps2-tz.c120 const uint32_t *oscclk; member
465 QList *oscclk; in make_scc() local
475 oscclk = qlist_new(); in make_scc()
477 qlist_append_int(oscclk, mmc->oscclk[i]); in make_scc()
479 qdev_prop_set_array(sccdev, "oscclk", oscclk); in make_scc()
1326 mmc->oscclk = an505_oscclk; in mps2tz_an505_class_init()
1360 mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ in mps2tz_an521_class_init()
1394 mmc->oscclk = an524_oscclk; in mps3tz_an524_class_init()
1433 mmc->oscclk = an524_oscclk; /* same as AN524 */ in mps3tz_an547_class_init()
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dcpu.c240 ulong oscclk, factor, pll; in get_tbclk() local
263 oscclk = gd->cpu_clk / factor; in get_tbclk()
267 return oscclk / 4; in get_tbclk()
269 return oscclk / 16; in get_tbclk()
/openbmc/u-boot/cmd/aspeed/
H A Dplltest.c106 //When the reference clock CLK25M count from 0 to 512, measure the OSCCLK counting value, then in cal_ast2600_28nm_pll_rate()
107 //OSCCLK frequency = CLK25M / 512 * (SCU320[29:16] + 1) in cal_ast2600_28nm_pll_rate()
170 //When the reference clock CLK25M count from 0 to 512, measure the OSCCLK counting value, then in cal_ast2600_13nm_pll_rate()
171 //OSCCLK frequency = CLK25M / 512 * (SCU320[29:16] + 1) in cal_ast2600_13nm_pll_rate()
/openbmc/linux/drivers/watchdog/
H A Drzg2l_wdt.c264 priv->osc_clk = devm_clk_get(&pdev->dev, "oscclk"); in rzg2l_wdt_probe()
266 return dev_err_probe(&pdev->dev, PTR_ERR(priv->osc_clk), "no oscclk"); in rzg2l_wdt_probe()
270 return dev_err_probe(&pdev->dev, -EINVAL, "oscclk rate is 0"); in rzg2l_wdt_probe()
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Daspeed,ast2600-pinctrl.yaml143 - OSCCLK
371 - OSCCLK

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