| /openbmc/qemu/hw/ppc/ |
| H A D | ppc405_uc.c | 357 static void ocm_update_mappings(Ppc405OcmState *ocm, in ocm_update_mappings() argument
361 trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc, in ocm_update_mappings()
362 ocm->isacntl, ocm->dsarc, ocm->dsacntl); in ocm_update_mappings()
364 if (ocm->isarc != isarc || in ocm_update_mappings()
365 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { in ocm_update_mappings()
366 if (ocm->isacntl & 0x80000000) { in ocm_update_mappings()
368 trace_ocm_unmap("ISA", ocm->isarc); in ocm_update_mappings()
369 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); in ocm_update_mappings()
375 &ocm->isarc_ram); in ocm_update_mappings()
378 if (ocm->dsarc != dsarc || in ocm_update_mappings()
[all …]
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| H A D | ppc405.h | 94 #define TYPE_PPC405_OCM "ppc405-ocm"
174 Ppc405OcmState ocm; member
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| H A D | trace-events | 164 …cm_isarc, uint32_t ocm_isacntl, uint32_t ocm_dsarc, uint32_t ocm_dsacntl) "OCM update ISA 0x%08" P…
165 ocm_map(const char* prefix, uint32_t isarc) "OCM map %s 0x%08" PRIx32
166 ocm_unmap(const char* prefix, uint32_t isarc) "OCM unmap %s 0x%08" PRIx32
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| /openbmc/linux/drivers/edac/ |
| H A D | zynqmp_edac.c | 3 * Xilinx ZynqMP OCM ECC Driver
70 #define EDAC_DEVICE "ZynqMP-OCM"
99 * struct edac_priv - OCM private instance data
100 * @baseaddr: Base address of the OCM
126 * @base: Pointer to the base address of the OCM
127 * @p: Pointer to the OCM ECC status structure
153 * @p: Pointer to the OCM ECC status structure
211 * @base: Pointer to the OCM base address
246 * echo <fault_count val> > /sys/kernel/debug/edac/ocm/inject_fault_count
248 * echo <bit_pos val> > /sys/kernel/debug/edac/ocm/inject_ce_bitpos
[all …]
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| H A D | Kconfig | 546 tristate "Xilinx ZynqMP OCM Controller"
550 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
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| /openbmc/linux/drivers/scsi/aic94xx/ |
| H A D | aic94xx_sds.c | 18 /* ---------- OCM stuff ---------- */
51 * OCM directory default
60 * OCM directory Entries default
108 * asd_read_ocm_seg - read an on chip memory (OCM) segment
111 * @offs: offset into OCM where to read from
134 ASD_DPRINTK("couldn't read ocm segment\n"); in asd_read_ocm_dir()
139 ASD_DPRINTK("no valid dir signature(%c%c) at start of OCM\n", in asd_read_ocm_dir()
144 asd_printk("unsupported major version of ocm dir:0x%x\n", in asd_read_ocm_dir()
153 * asd_write_ocm_seg - write an on chip memory (OCM) segment
156 * @offs: offset into OCM to write to
[all …]
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| H A D | aic94xx_hwi.c | 174 /* MBAR1 will point to OCM (On Chip Memory) */ in asd_init_sw()
630 asd_printk("couldn't read ocm(%d)\n", err); in asd_init_hw()
632 * couldn't read the OCM. */ in asd_init_hw()
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | xlnx,zynqmp-ocmc-1.0.yaml | 7 title: Xilinx Zynqmp OCM(On-Chip Memory) Controller
14 The OCM supports 64-bit wide ECC functionality to detect multi-bit errors
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| /openbmc/u-boot/post/ |
| H A D | tests.c | 50 "OCM test",
51 "ocm",
52 "This test checks on chip memory (OCM).",
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| /openbmc/u-boot/arch/arm/mach-zynqmp/ |
| H A D | Kconfig | 81 bool "Define TCM and OCM memory in MMU Table"
84 This option if enabled defines the TCM and OCM memory and its
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| H A D | mp.c | 254 * OCM will be probably occupied by ATF in cpu_release()
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| /openbmc/linux/arch/powerpc/boot/dts/ |
| H A D | bluestone.dts | 95 OCM: ocm@400040000 { label
96 compatible = "ibm,ocm";
137 descriptor-memory = "ocm";
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| /openbmc/u-boot/cmd/ |
| H A D | fpga.c | 451 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
455 "The auth-OCM/DDR flag specifies to perform authentication\n"
456 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
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| /openbmc/qemu/docs/system/arm/ |
| H A D | xlnx-zynq.rst | 16 - OCM 256KB
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| H A D | xlnx-versal-virt.rst | 32 - OCM (256KB of On Chip Memory)
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| /openbmc/linux/Documentation/devicetree/bindings/reset/ |
| H A D | zynq-reset.txt | 60 448: ocm reset
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| /openbmc/linux/drivers/bus/ |
| H A D | omap_l3_smx.h | 265 /* OCM RAM TA */
267 /* OCM ROM TA */
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| /openbmc/linux/drivers/net/ethernet/qlogic/qlcnic/ |
| H A D | qlcnic_minidump.c | 233 struct __ocm ocm; member
547 struct __ocm *ocm = &entry->region.ocm; in qlcnic_dump_ocm() local
549 addr = adapter->ahw->pci_base0 + ocm->read_addr; in qlcnic_dump_ocm()
550 for (i = 0; i < ocm->no_ops; i++) { in qlcnic_dump_ocm()
553 addr += ocm->read_addr_stride; in qlcnic_dump_ocm()
555 return ocm->no_ops * sizeof(u32); in qlcnic_dump_ocm()
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| /openbmc/u-boot/include/configs/ |
| H A D | zynq-common.h | 315 /* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
318 /* On the top of OCM space */
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| H A D | xilinx_zynqmp.h | 227 /* Just random location in OCM */
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| /openbmc/linux/arch/arm/boot/dts/xilinx/ |
| H A D | zynq-zc702.dts | 67 ocm: sram@fffc0000 { label
73 ocm-sram@0 {
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| /openbmc/linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | xlnx,zynqmp-r5fss.yaml | 80 the RPU can execute instructions and access data from the OCM memory,
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| /openbmc/linux/drivers/remoteproc/ |
| H A D | xlnx_r5_remoteproc.c | 344 * from 0xFFFF_0000 (HIVEC) which is mapped in the OCM (On-Chip Memory) in zynqmp_r5_rproc_start()
350 * and jitter. Also, if the OCM is secured and the Cortex-R5F processor in zynqmp_r5_rproc_start()
352 * HIVEC exception vectors in the OCM. in zynqmp_r5_rproc_start()
358 bootmem == PM_RPU_BOOTMEM_HIVEC ? "OCM" : "TCM"); in zynqmp_r5_rproc_start()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | zynq-zc702.dts | 67 ocm: sram@fffc0000 { label
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| /openbmc/linux/drivers/scsi/qla2xxx/ |
| H A D | qla_nx2.h | 344 /* Read OCM */
|