| /openbmc/linux/Documentation/PCI/ |
| H A D | msi-howto.rst | 15 This guide describes the basics of Message Signaled Interrupts (MSIs),
18 try if a device doesn't support MSIs.
21 What are MSIs?
36 Why use MSIs?
39 There are three reasons why using MSIs can give an advantage over
45 a whole. MSIs are never shared, so this problem cannot arise.
54 Using MSIs avoids this problem as the interrupt-generating write cannot
61 MSIs, a device can support more interrupts, allowing each interrupt
69 How to use MSIs
74 support MSIs correctly, and for those machines, the APIs described below
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | msi.txt | 4 Message Signaled Interrupts (MSIs) are a class of interrupts generated by a
7 MSIs were originally specified by PCI (and are used with PCIe), but may also be
12 MSIs are distinguished by some combination of:
57 MSI clients are devices which generate MSIs. For each MSI they wish to
67 This property is unordered, and MSIs may be allocated from any combination of
70 If a device has restrictions on the allocation of MSIs, these restrictions
75 and the set of MSIs they can potentially generate.
112 /* Can only generate MSIs to msi_a */
121 * Can generate MSIs to either A or B.
131 * Can generate MSIs to all of the MSI controllers.
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| H A D | marvell,sei.txt | 11 MSIs.
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| /openbmc/qemu/include/hw/pci-host/ |
| H A D | pnv_phb3.h | 20 * PHB3 XICS Source for MSIs
38 void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
40 void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data,
42 void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val);
43 void pnv_phb3_msi_pic_print_info(Phb3MsiState *msis, GString *buf);
155 Phb3MsiState msis; member
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| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_irq_kms.c | 234 * MSIs should be enabled on a particular chip (all asics).
235 * Returns true if MSIs should be enabled, false if MSIs
244 /* MSIs don't work on AGP */ in radeon_msi_ok()
250 * of address for "64-bit" MSIs which breaks on some platforms, notably in radeon_msi_ok()
265 /* HP RS690 only seems to work with MSIs. */ in radeon_msi_ok()
271 /* Dell RS690 only seems to work with MSIs. */ in radeon_msi_ok()
277 /* Dell RS690 only seems to work with MSIs. */ in radeon_msi_ok()
283 /* Gateway RS690 only seems to work with MSIs. */ in radeon_msi_ok()
289 /* try and enable MSIs by default on all RS690s */ in radeon_msi_ok()
300 /* APUs work fine with MSIs */ in radeon_msi_ok()
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | apple,pcie.yaml | 26 MSIs are handled by the PCIe controller and translated into regular
27 interrupts. A range of 32 MSIs is provided. These 32 MSIs can be
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| /openbmc/linux/arch/powerpc/platforms/pseries/ |
| H A D | msi.c | 88 pr_debug("rtas_msi: Setting MSIs to 0 failed!\n"); in rtas_disable_msi()
131 pr_debug("rtas_msi: %s requests < %d MSIs\n", prop_name, nvec); in check_req()
308 * use the remainder as spare MSIs for anyone that wants them. */ in msi_quota_for_device()
331 * fact that we using RTAS for MSIs, we don't have the 32 bit MSI RTAS in rtas_hack_32bit_msi_gen2()
644 pr_err("PCI: failed to find MSIs for bridge %pOF (domain %d)\n", in pseries_msi_allocate_domains()
664 /* No LSI -> leave MSIs (if any) configured */ in rtas_msi_pci_irq_fixup()
670 /* No MSI -> MSIs can't have been assigned by fw, leave LSI */ in rtas_msi_pci_irq_fixup()
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| /openbmc/linux/Documentation/powerpc/ |
| H A D | pci_iov_resource_on_powernv.rst | 24 partitions (i.e., filtering of DMA, MSIs etc.) and to provide a mechanism
33 return all 1's value. MSIs are also blocked. There's a bit more state that
52 For DMA, MSIs and inbound PCIe error messages, we have a table (in
63 - For MSIs, we have two windows in the address space (one at the top of
91 reserved for MSIs but this is not a problem at this point; we just
152 "master PE" which is the one used for DMA, MSIs, etc., and "secondary
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-loongson-pch-msi.c | 23 u32 irq_first; /* The vector number that MSIs starts */
24 u32 num_irqs; /* The number of vectors for MSIs */
209 pr_debug("Registering %d MSIs, starting at %d\n", in pch_msi_init()
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| H A D | irq-alpine-msi.c | 34 u32 spi_first; /* The SGI number that MSIs start */
35 u32 num_spis; /* The number of SGIs for MSIs */
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| H A D | irq-gic-v3-its-platform-msi.c | 65 /* Allocate at least 32 MSIs, and always as a power of 2 */ in its_pmsi_prepare()
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| H A D | irq-gic-v3-its-fsl-mc-msi.c | 63 /* Allocate at least 32 MSIs, and always as a power of 2 */ in its_fsl_mc_msi_prepare()
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| /openbmc/qemu/hw/pci-host/ |
| H A D | pnv_phb3.c | 410 pnv_phb3_msi_update_config(&phb->msis, comp, count - PNV_PHB3_NUM_LSI); in pnv_phb3_remap_irqs()
565 pnv_phb3_msi_ffi(&phb->msis, val); in pnv_phb3_reg_write()
920 pnv_phb3_msi_send(&ds->phb->msis, addr, data, ds->pe_num); in pnv_phb3_msi_write()
988 object_initialize_child(obj, "msi", &phb->msis, TYPE_PHB3_MSI); in pnv_phb3_instance_init()
1049 object_property_set_link(OBJECT(&phb->msis), "phb", OBJECT(phb), in pnv_phb3_realize()
1051 object_property_set_link(OBJECT(&phb->msis), "xics", OBJECT(pnv), in pnv_phb3_realize()
1053 object_property_set_int(OBJECT(&phb->msis), "nr-irqs", PHB3_MAX_MSI, in pnv_phb3_realize()
1055 if (!qdev_realize(DEVICE(&phb->msis), NULL, errp)) { in pnv_phb3_realize()
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| /openbmc/linux/arch/x86/platform/uv/ |
| H A D | uv_irq.c | 123 * on the specified blade to allow the sending of MSIs to the specified CPU.
133 * Disable the specified MMR located on the specified blade so that MSIs are
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| /openbmc/linux/include/asm-generic/ |
| H A D | msi.h | 34 /* Device generating MSIs is proxying for another device */
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| /openbmc/linux/Documentation/accel/qaic/ |
| H A D | qaic.rst | 18 non-empty and generate MSIs at a rate equivalent to the speed of the
21 MSIs per second. It has been observed that most systems cannot tolerate this
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| /openbmc/linux/Documentation/virt/kvm/devices/ |
| H A D | mpic.rst | 30 MSIs may be signaled by using this attribute group to write
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| /openbmc/qemu/linux-headers/linux/ |
| H A D | vfio_zdev.h | 50 __u16 noi; /* Maximum number of MSIs */
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| /openbmc/linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | brcm,iproc-flexrm-mbox.txt | 15 The FlexRM engine will send MSIs (instead of wired
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| /openbmc/linux/include/uapi/linux/ |
| H A D | vfio_zdev.h | 50 __u16 noi; /* Maximum number of MSIs */
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| /openbmc/linux/drivers/base/ |
| H A D | platform-msi.c | 255 * @dev: The device generating the MSIs
256 * @nvec: The number of MSIs that need to be allocated
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| /openbmc/linux/drivers/pci/msi/ |
| H A D | msi.c | 22 * @nvec: how many MSIs have been requested?
40 * You can't ask to have 0 or less MSIs configured. in pci_msi_supported()
291 /* Lies, damned lies, and MSIs */ in msi_setup_msi_desc()
373 /* All MSIs are unmasked by default; mask them all */ in msi_capability_init()
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| /openbmc/linux/arch/powerpc/platforms/pasemi/ |
| H A D | msi.c | 92 * few MSIs for someone, but restrictions will apply to how the in pasemi_msi_setup_msi_irqs()
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| /openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | msi-pic.txt | 19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
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| /openbmc/linux/arch/riscv/include/asm/ |
| H A D | kvm_aia.h | 27 /* Number of MSIs */
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