Searched full:mr6 (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | fsl_ddr_gen4.c | 61 u32 mr6; in fsl_ddr_set_memctl_regs() local
373 mr6 = (regs->ddr_sdram_mode_10 >> 16) | in fsl_ddr_set_memctl_regs()
378 temp32 = mr6 | vref_seq[0]; in fsl_ddr_set_memctl_regs()
382 debug("MR6 = 0x%08x\n", temp32); in fsl_ddr_set_memctl_regs()
383 temp32 = mr6 | vref_seq[1]; in fsl_ddr_set_memctl_regs()
387 debug("MR6 = 0x%08x\n", temp32); in fsl_ddr_set_memctl_regs()
388 temp32 = mr6 | vref_seq[2]; in fsl_ddr_set_memctl_regs()
392 debug("MR6 = 0x%08x\n", temp32); in fsl_ddr_set_memctl_regs()
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr-props.yaml | 24 (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are
39 Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
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| /openbmc/linux/drivers/memory/ |
| H A D | brcmstb_dpfe.c | 802 u32 mr5, mr6, mr7, mr8, err; in show_vendor() local
815 mr6 = (readl_relaxed(info + DRAM_VENDOR_MR6) >> DRAM_VENDOR_SHIFT) & in show_vendor()
823 return sprintf(buf, "%#x %#x %#x %#x %#x\n", mr5, mr6, mr7, mr8, err); in show_vendor()
832 u32 mr4, mr5, mr6, mr7, mr8, err; in show_dram() local
841 mr6 = response[MSG_ARG0 + 2] & DRAM_DDR_INFO_MASK; in show_dram()
846 return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7, in show_dram()
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| /openbmc/u-boot/drivers/ram/aspeed/ |
| H A D | sdram_phy_ast2600.h | 100 * MR6[6] VrefDQ training range
130 /* MR3 ~ MR6 */
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