| #
23bcb5d2 |
| 25-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: add option for DRAM ODT 80 ohm
Add CONFIG_ASPEED_DDR4_DRAM_ODT80 to change the DRAM ODT to 80 ohm. The
default value keeps on 48 ohm.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.
ram: ast2600: add option for DRAM ODT 80 ohm
Add CONFIG_ASPEED_DDR4_DRAM_ODT80 to change the DRAM ODT to 80 ohm. The
default value keeps on 48 ohm.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I8a0775309fac689a607ed4a3077b9eded61d8828
show more ...
|
| #
e2ef8286 |
| 22-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: fix typo of CONFIG_ASPEED_DDR4_DRAM_RON_48
Fix the typo for missing "CONFIG_" of CONFIG_ASPEED_DDR4_DRAM_RON_48
Fixes: cb2cc580a14a ("ram: ast2600: add option to configure DRAM output
ram: ast2600: fix typo of CONFIG_ASPEED_DDR4_DRAM_RON_48
Fix the typo for missing "CONFIG_" of CONFIG_ASPEED_DDR4_DRAM_RON_48
Fixes: cb2cc580a14a ("ram: ast2600: add option to configure DRAM output impedance")
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I7cc4a9ac904e5562a8a5a4d7075b3cd5fe1f5810
show more ...
|
| #
16261a32 |
| 22-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Revert "Revert "ram: ast2600: add option for write data eye training result offset""
This reverts commit 260266628ecd7052a5d0a44f87940fea2c6dbaf4.
Reason for revert: rebase dram driver
Change-Id:
Revert "Revert "ram: ast2600: add option for write data eye training result offset""
This reverts commit 260266628ecd7052a5d0a44f87940fea2c6dbaf4.
Reason for revert: rebase dram driver
Change-Id: If9644975969922093d6be6d32f30303e4b165d07
show more ...
|
| #
26026662 |
| 22-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Revert "ram: ast2600: add option for write data eye training result offset"
This reverts commit 841e08048f8fde541c710d2cd3b9982e1523eb81.
Reason for revert: rebase sdram_ast2600 driver
Change-Id:
Revert "ram: ast2600: add option for write data eye training result offset"
This reverts commit 841e08048f8fde541c710d2cd3b9982e1523eb81.
Reason for revert: rebase sdram_ast2600 driver
Change-Id: Ic6ada37982099c7f0750cffd862c65ff29fef9a5
show more ...
|
| #
841e0804 |
| 22-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: add option for write data eye training result offset
Add an option to fine-tune the DDR PHY write data eye training result.
The default value is 0x10.
Signed-off-by: Dylan Hung <dylan
ram: ast2600: add option for write data eye training result offset
Add an option to fine-tune the DDR PHY write data eye training result.
The default value is 0x10.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: If95fc958267ce18e85d686f3f33fe0858cdc532b
show more ...
|
| #
812eb0bb |
| 21-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: remove CA and read data eye manual delay
According to the PHY vendor:
phyr0a8[31:24] - CA training manual mode delay, shall be 0
phyr198[15:8] - read data eye training result manual of
ram: ast2600: remove CA and read data eye manual delay
According to the PHY vendor:
phyr0a8[31:24] - CA training manual mode delay, shall be 0
phyr198[15:8] - read data eye training result manual offset, shall be 0
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I6aa6d4a23e7f28306af44bfba43e521383c9070b
show more ...
|
| #
a77d558c |
| 21-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: align the RL and WL setting
Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Ch
ram: ast2600: align the RL and WL setting
Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I9151ef465ddb45b96bb0c5d61c01d516a92127c4
show more ...
|
| #
323f39fb |
| 21-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: use macro to represent DRAM MR
Use macro to represent DRAM mode registers. Both DDR-PHY and DDR
controller have their own registers for MR configuration, use the same
values for both
ram: ast2600: use macro to represent DRAM MR
Use macro to represent DRAM mode registers. Both DDR-PHY and DDR
controller have their own registers for MR configuration, use the same
values for both side.
Also, this commit modifies the default RTT and RON setting
RTT_WR: disable
RTT_NOM: 48 ohm
RTT_PARK: 48 ohm
DRAM output driver impedance: 34 ohm
PHY Ron: 34 ohm
PHY ODT: 80 ohm
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I38be1ef106a914dcfb5da3149ff59ca6ec4f3fbb
show more ...
|
| #
cb2cc580 |
| 21-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: add option to configure DRAM output impedance
The DRAM output impedance is controlled by MR1[A2:A1]. Add an option to
make it configurable.
Signed-off-by: Dylan Hung <dylan_hung@aspe
ram: ast2600: add option to configure DRAM output impedance
The DRAM output impedance is controlled by MR1[A2:A1]. Add an option to
make it configurable.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I0f2c5e9bd196a2dbb81e5a8a588f33079340a7ae
show more ...
|
| #
dd3a6e11 |
| 21-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: add option for PHY ODT 80 ohm
Add option to select PHY ODT 80 ohm
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Ia0e862de4f223e675414428abe1cc0cfeea8a1b9
|
| #
43925ad7 |
| 21-Sep-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: ast2600: add macro to represent PHY_RON setting
Use macro to represent PHY Ron setting in PHY registers.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Iaf540e239f4be9ae4ad38
ram: ast2600: add macro to represent PHY_RON setting
Use macro to represent PHY Ron setting in PHY registers.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Iaf540e239f4be9ae4ad385cdfdf72c42aafd0c0c
show more ...
|
|
Revision tags: v00.04.11 |
|
| #
b415f713 |
| 17-May-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
ram: aspeed: add AST2600 ODT configuration
PHY side: 1e6e0130[10:8]
- b'100 = 60 ohm
- b'101 = 48 ohm
- b'110 = 40 ohm (default)
DRAM side: 1e6e0158[10:8] & 1e6e0020[26:24]
- b'001 = 60 ohm
- b'101
ram: aspeed: add AST2600 ODT configuration
PHY side: 1e6e0130[10:8]
- b'100 = 60 ohm
- b'101 = 48 ohm
- b'110 = 40 ohm (default)
DRAM side: 1e6e0158[10:8] & 1e6e0020[26:24]
- b'001 = 60 ohm
- b'101 = 48 ohm
- b'011 = 40 ohm (default)
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I38883cbdd6de5a0f042573506c88a10f16d14f83
show more ...
|
|
Revision tags: v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03 |
|
| #
af78b2d2 |
| 09-Sep-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] fine tune DDR-PHY param
to bring up Nanya memory chip
|
|
Revision tags: v00.02.02, v00.02.01 |
|
| #
827cd61a |
| 11-Jul-2019 |
Chia-Wei, Wang <chiawei_wang@aspeedtech.com> |
Merge branch 'feature/aspeed-build' into aspeed-dev-v2019.04
|
| #
c7ebc30f |
| 11-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
Merge branch 'feature/revise_dram' into aspeed-dev-v2019.04
|
| #
79088fd5 |
| 09-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] add configs for DDR4_800 and 1600
|
| #
975e079c |
| 09-Jul-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] DDR4 can run on 1600
|
|
Revision tags: v2019.07 |
|
| #
01458b74 |
| 04-Jul-2019 |
Chia-Wei, Wang <chiawei_wang@aspeedtech.com> |
Merge branch 'feature-mpcore' into aspeed-dev-v2019.04
|
| #
befc1c99 |
| 02-Jul-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
Merge branch 'ryan_port' into aspeed-dev-v2019.04
|
| #
6b2c0f08 |
| 29-Jun-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] merge featute/ast2600_dram for realchip
|
| #
47ff9101 |
| 29-Jun-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] revise ast2600 default DRAM config
|
| #
7579eef2 |
| 27-Jun-2019 |
Chia-Wei, Wang <chiawei_wang@aspeedtech.com> |
Merge branch 'spl_ast2600' into aspeed-dev-v2019.04
|
| #
2482004e |
| 27-Jun-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] set default GUC 1600M setting
as the default DDR PHY table
|
| #
465dd93d |
| 26-Jun-2019 |
Dylan Hung <dylan_hung@aspeedtech.com> |
[update] add PHY tables
|
|
Revision tags: v00.02.00 |
|
| #
e08cd9d7 |
| 05-Jun-2019 |
ryan_chen <ryan_chen@aspeedtech.com> |
Merge branch 'ryan_port' into aspeed-dev-v2019.04
# Conflicts:
# configs/evb-ast2600_defconfig
|