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/openbmc/linux/sound/drivers/mpu401/
H A Dmpu401_uart.c4 * Routines for control of MPU-401 in UART mode
6 * MPU-401 supports UART mode which is not capable generate transmit
12 * are port and mmio. For other kind of I/O, set mpu->read and
13 * mpu->write to your own I/O functions.
28 MODULE_DESCRIPTION("Routines for control of MPU-401 in UART mode");
31 static void snd_mpu401_uart_input_read(struct snd_mpu401 * mpu);
32 static void snd_mpu401_uart_output_write(struct snd_mpu401 * mpu);
38 #define snd_mpu401_input_avail(mpu) \ argument
39 (!(mpu->read(mpu, MPU401C(mpu)) & MPU401_RX_EMPTY))
40 #define snd_mpu401_output_ready(mpu) \ argument
[all …]
H A Dmpu401.c3 * Driver for generic MPU-401 boards (UART mode only)
18 MODULE_DESCRIPTION("MPU-401 UART");
27 static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT; /* MPU-401 port number */
28 static int irq[SNDRV_CARDS] = SNDRV_DEFAULT_IRQ; /* MPU-401 IRQ */
32 MODULE_PARM_DESC(index, "Index value for MPU-401 device.");
34 MODULE_PARM_DESC(id, "ID string for MPU-401 device.");
36 MODULE_PARM_DESC(enable, "Enable MPU-401 device.");
39 MODULE_PARM_DESC(pnp, "PnP detection for MPU-401 device.");
42 MODULE_PARM_DESC(port, "Port # for MPU-401 device.");
44 MODULE_PARM_DESC(irq, "IRQ # for MPU-401 device.");
[all …]
/openbmc/linux/sound/isa/msnd/
H A Dmsnd_midi.c5 * Routines for control of MPU-401 in UART mode
7 * MPU-401 supports UART mode which is not capable generate transmit
43 struct snd_msndmidi *mpu; in snd_msndmidi_input_open() local
47 mpu = substream->rmidi->private_data; in snd_msndmidi_input_open()
49 mpu->substream_input = substream; in snd_msndmidi_input_open()
51 snd_msnd_enable_irq(mpu->dev); in snd_msndmidi_input_open()
53 snd_msnd_send_dsp_cmd(mpu->dev, HDEX_MIDI_IN_START); in snd_msndmidi_input_open()
54 set_bit(MSNDMIDI_MODE_BIT_INPUT, &mpu->mode); in snd_msndmidi_input_open()
60 struct snd_msndmidi *mpu; in snd_msndmidi_input_close() local
62 mpu = substream->rmidi->private_data; in snd_msndmidi_input_close()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/omap/
H A Dmpu.txt1 * TI - MPU (Main Processor Unit) subsystem
3 The MPU subsystem contain one or several ARM cores
5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.
8 - compatible : Should be "ti,omap3-mpu" for OMAP3
9 Should be "ti,omap4-mpu" for OMAP4
10 Should be "ti,omap5-mpu" for OMAP5
11 - ti,hwmods: "mpu"
27 mpu {
28 compatible = "ti,omap5-mpu";
29 ti,hwmods = "mpu"
[all …]
/openbmc/linux/include/sound/
H A Dmpu401.h6 * Header file for MPU-401 and compatible cards
14 #define MPU401_HW_SB 2 /* SoundBlaster MPU-401 UART */
15 #define MPU401_HW_ES1688 3 /* AudioDrive ES1688 MPU-401 UART */
19 #define MPU401_HW_ES18XX 7 /* AudioDrive ES18XX MPU-401 UART */
27 #define MPU401_HW_CMIPCI 15 /* CMIPCI MPU-401 UART */
61 unsigned long port; /* base port of MPU-401 chip */
64 int irq; /* IRQ number of MPU-401 chip */
69 int (*open_input) (struct snd_mpu401 * mpu);
70 void (*close_input) (struct snd_mpu401 * mpu);
71 int (*open_output) (struct snd_mpu401 * mpu);
[all …]
/openbmc/linux/sound/isa/wavefront/
H A Dwavefront_midi.c8 * Note that there is also an MPU-401 emulation (actually, a UART-401
25 * something other than 0 and 1 if the CS4232 UART/MPU-401 interface
115 snd_wavefront_mpu_id mpu; in snd_wavefront_midi_output_write() local
191 mpu = midi->output_mpu ^ mask; in snd_wavefront_midi_output_write()
193 if ((midi->mode[mpu] & MPU401_MODE_OUTPUT) == 0) { in snd_wavefront_midi_output_write()
197 if (snd_rawmidi_transmit_empty(midi->substream_output[mpu])) in snd_wavefront_midi_output_write()
200 if (mpu != midi->output_mpu) { in snd_wavefront_midi_output_write()
201 write_data(midi, mpu == internal_mpu ? in snd_wavefront_midi_output_write()
204 midi->output_mpu = mpu; in snd_wavefront_midi_output_write()
205 } else if (snd_rawmidi_transmit(midi->substream_output[mpu], &midi_byte, 1) == 1) { in snd_wavefront_midi_output_write()
[all …]
H A Dwavefront.c61 MODULE_PARM_DESC(cs4232_mpu_port, "port # for CS4232 MPU-401 interface.");
63 MODULE_PARM_DESC(cs4232_mpu_irq, "IRQ # for CS4232 MPU-401 interface.");
71 MODULE_PARM_DESC(use_cs4232_midi, "Use CS4232 MPU-401 interface (inaccessibly located inside your c…
114 acard->mpu = pnp_request_card_device(card, id->devs[2].id, NULL); in snd_wavefront_pnp()
115 if (acard->mpu == NULL) in snd_wavefront_pnp()
166 /* CS4232 MPU initialization. Configure this only if in snd_wavefront_pnp()
173 pdev = acard->mpu; in snd_wavefront_pnp()
184 snd_printk (KERN_INFO "CS4232 MPU: port=0x%lx, irq=%i\n", in snd_wavefront_pnp()
275 snd_wavefront_mpu_id mpu) in snd_wavefront_new_midi() argument
293 if (mpu == internal_mpu) { in snd_wavefront_new_midi()
[all …]
/openbmc/linux/sound/pci/emu10k1/
H A Demumpu401.c4 * Routines for control of EMU10K1 MPU-401 in UART mode
16 struct snd_emu10k1_midi *mpu, int idx) in mpu401_read() argument
19 return (unsigned char)snd_emu10k1_ptr_read(emu, mpu->port + idx, 0); in mpu401_read()
21 return inb(emu->port + mpu->port + idx); in mpu401_read()
25 struct snd_emu10k1_midi *mpu, int data, int idx) in mpu401_write() argument
28 snd_emu10k1_ptr_write(emu, mpu->port + idx, 0, data); in mpu401_write()
30 outb(data, emu->port + mpu->port + idx); in mpu401_write()
33 #define mpu401_write_data(emu, mpu, data) mpu401_write(emu, mpu, data, 0) argument
34 #define mpu401_write_cmd(emu, mpu, data) mpu401_write(emu, mpu, data, 1) argument
35 #define mpu401_read_data(emu, mpu) mpu401_read(emu, mpu, 0) argument
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dcpuidle34xx.c49 * OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
50 * inactive. This in turn prevents the MPU DPLL from entering autoidle
273 .desc = "MPU ON + CORE ON",
281 .desc = "MPU ON + CORE ON",
289 .desc = "MPU RET + CORE ON",
297 .desc = "MPU OFF + CORE ON",
305 .desc = "MPU RET + CORE RET",
313 .desc = "MPU OFF + CORE RET",
321 .desc = "MPU OFF + CORE OFF",
343 .desc = "MPU ON + CORE ON",
[all …]
H A Domap4-common.c60 * data writes from the MPU. These asynchronous bridges can be found on
61 * paths between the MPU to EMIF, and the MPU to L3 interconnects.
74 * The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
95 * Async bridges can be found on paths between MPU to EMIF and MPU to L3
107 * In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
112 * operates on both the MPU->MA->EMIF path but also the MPU->OCP path
132 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu"); in omap4_sram_init()
294 { .compatible = "ti,omap4-wugen-mpu", },
295 { .compatible = "ti,omap5-wugen-mpu", },
H A Dclockdomains3xxx_data.c70 /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
88 /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
124 /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
135 /* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
143 /* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
157 /* 3430: PM_WKDEP_NEON: MPU */
165 /* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
177 /* 3430: CM_SLEEPDEP_PER: MPU, IVA */
189 /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
201 /* 3430: CM_SLEEPDEP_CAM: MPU */
[all …]
/openbmc/qemu/hw/arm/
H A Domap1.c104 /* MPU OS timers */
292 "omap-mpu-timer", 0x100); in omap_mpu_timer_init()
728 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) in omap_ulpd_pm_reset() argument
730 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; in omap_ulpd_pm_reset()
731 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; in omap_ulpd_pm_reset()
732 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; in omap_ulpd_pm_reset()
733 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; in omap_ulpd_pm_reset()
734 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; in omap_ulpd_pm_reset()
735 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; in omap_ulpd_pm_reset()
736 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; in omap_ulpd_pm_reset()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dti,omap4-wugen-mpu5 is also referred to as "WUGEN-MPU", hence the name of the binding.
9 - compatible : should contain at least "ti,omap4-wugen-mpu" or
10 "ti,omap5-wugen-mpu"
26 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dmpu_v7r.c18 /* MPU Type register definitions */
26 * The Memory Protection Unit(MPU) allows to partition memory into regions
28 * of MPU a default map[1] will take effect. make sure to run this code
66 /* MPU Region Number Register */ in mpu_config()
69 /* MPU Region Base Address Register */ in mpu_config()
72 /* MPU Region Size and Enable Register */ in mpu_config()
79 /* MPU Region Access Control Register */ in mpu_config()
/openbmc/linux/arch/arm/mm/
H A Dpmsa-v7.c14 #include <asm/mpu.h>
137 /* ARMv7-M only supports a unified MPU, so I-side operations are nop */
230 /* MPU initialisation functions */
301 pr_debug("MPU: base %pa size %pa disable subregions: %*pbl\n", in pmsav7_adjust_lowmem_bounds()
306 pr_warn("Truncating memory from %pa to %pa (MPU region constraints)", in pmsav7_adjust_lowmem_bounds()
354 /* If the MPU is non-unified, we use the larger of the two minima*/ in __mpu_min_region_order()
360 isb(); /* Ensure that MPU region operations have completed */ in __mpu_min_region_order()
372 /* We kept a region free for probing resolution of MPU regions*/ in mpu_setup_region()
418 * Set up default MPU regions, doing nothing if there is no MPU
424 /* Setup MPU (order is important) */ in pmsav7_setup()
[all …]
/openbmc/u-boot/board/ti/dra7xx/
H A Devm.c375 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
376 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
377 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
378 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
379 .mpu.pmic = &tps659038,
380 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
423 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
424 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
425 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
426 .mpu.addr = LP87565_REG_ADDR_BUCK01,
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
65 * dpll locked at 1200 MHz - MPU clk at 600 MHz
163 .mpu = mpu_dpll_params_1200mhz,
177 .mpu = mpu_dpll_params_1200mhz,
191 .mpu = mpu_dpll_params_1200mhz,
205 .mpu = mpu_dpll_params_1400mhz,
219 .mpu = mpu_dpll_params_1600mhz,
265 .mpu.value[OPP_NOM] = 1325,
266 .mpu.addr = SMPS_REG_ADDR_VCORE1,
[all …]
/openbmc/linux/arch/arm/
H A DKconfig-nommu57 bool 'Use the ARM v7 PMSA Compliant MPU'
62 Unit (MPU) that defines the type and permissions for regions of
65 If your CPU has an MPU then you should choose 'y' here unless you
66 know that you do not want to use the MPU.
/openbmc/qemu/include/hw/arm/
H A Darmv7m.h56 * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
59 * + Property "mpu-s-regions": number of Secure MPU regions (default is
61 * value as mpu-ns-regions if the CPU implements the Security Extension)
/openbmc/linux/arch/arm/kernel/
H A Dvmlinux-xip.lds.S16 #include <asm/mpu.h>
185 * space spawns multiple MPU regions thus it is likely we run in
186 * situation when we are reprogramming MPU region we run on with
188 * as we update MPU settings we'd immediately try to execute straight
194 ASSERT(!(_xiprom & (SZ_1M - 1)), "XIP start address may cause MPU programming issues")
195 ASSERT(!(_exiprom & (SZ_128K - 1)), "XIP end address may cause MPU programming issues")
/openbmc/linux/drivers/macintosh/
H A Dwindfarm_ad7417_sensor.c31 const struct mpu_data *mpu; member
84 *value = (raw * (s32)pv->mpu->mdiode + in wf_ad7417_adc_convert()
85 ((s32)pv->mpu->bdiode << 12)) >> 2; in wf_ad7417_adc_convert()
235 const struct mpu_data *mpu; in wf_ad7417_probe() local
257 mpu = wf_get_mpu(cpu_nr); in wf_ad7417_probe()
258 if (!mpu) { in wf_ad7417_probe()
259 dev_err(&client->dev, "Failed to retrieve MPU data\n"); in wf_ad7417_probe()
271 pv->mpu = mpu; in wf_ad7417_probe()
/openbmc/u-boot/board/eets/pdu001/
H A Dboard.c132 * TPS65910 PMIC. For all MPU frequencies we support we use a CORE in set_mpu_and_core_voltage()
133 * voltage of 1.1375V. For MPU voltage we need to switch based on in set_mpu_and_core_voltage()
138 * Depending on MPU clock and PG we will need a different VDD in set_mpu_and_core_voltage()
144 /* first update the MPU voltage */ in set_mpu_and_core_voltage()
147 debug("failed to set MPU voltage\n"); in set_mpu_and_core_voltage()
149 debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR); in set_mpu_and_core_voltage()
202 /* Set MPU Frequency to what we detected now that voltages are set */ in am33xx_spl_board_init()
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Dti-smartreflex.txt10 "ti,omap3-smartreflex-mpu-iva"
12 "ti,omap4-smartreflex-mpu"
43 compatible = "ti,omap4-smartreflex-mpu";
/openbmc/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
H A Dcake.json349 "name": "Create CAKE with overhead and mpu",
360 "cmdUnderTest": "$TC qdisc add dev $DUMMY handle 1: root cake overhead 128 mpu 256",
363 …iffserv3 triple-isolate nonat nowash no-ack-filter split-gso rtt 100ms noatm overhead 128 mpu 256",
418 "name": "Replace CAKE with mpu",
428 "$TC qdisc add dev $DUMMY handle 1: root cake overhead 128 mpu 256"
430 "cmdUnderTest": "$TC qdisc replace dev $DUMMY handle 1: root cake mpu 128",
433 …iffserv3 triple-isolate nonat nowash no-ack-filter split-gso rtt 100ms noatm overhead 128 mpu 128",
442 "name": "Change CAKE with mpu",
452 "$TC qdisc add dev $DUMMY handle 1: root cake overhead 128 mpu 256"
454 "cmdUnderTest": "$TC qdisc change dev $DUMMY handle 1: root cake mpu 128",
[all …]
/openbmc/linux/Documentation/arch/arm/omap/
H A Domap_pm.rst34 1. Set the maximum MPU wakeup latency::
87 set_max_mpu_wakeup_lat() function to constrain the MPU wakeup
92 /* Limit MPU wakeup latency */
119 CPUFreq expresses target MPU performance levels in terms of MPU
121 specialized cases to convert that input information (OPPs/MPU

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