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/openbmc/linux/arch/arm/kernel/
H A Dsleep.S11 * Implementation of MPIDR hash algorithm through shifting
18 * @mpidr: register containing MPIDR value
19 * @mask: register containing MPIDR mask
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
27 * u32 mpidr_masked = mpidr & mask;
33 * Input registers: rs0, rs1, rs2, mpidr, mask
36 (eg: a macro instance with mpidr = r1 and dst = r1 is invalid)
38 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
39 and \mpidr, \mpidr, \mask @ mask out MPIDR bits
40 and \dst, \mpidr, #0xff @ mask=aff0
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H A Dtopology.c188 unsigned int mpidr; in store_cpu_topology() local
193 mpidr = read_cpuid_mpidr(); in store_cpu_topology()
196 if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) { in store_cpu_topology()
202 if (mpidr & MPIDR_MT_BITMASK) { in store_cpu_topology()
204 cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in store_cpu_topology()
205 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); in store_cpu_topology()
206 cpuid_topo->package_id = MPIDR_AFFINITY_LEVEL(mpidr, 2); in store_cpu_topology()
210 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in store_cpu_topology()
211 cpuid_topo->package_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); in store_cpu_topology()
226 pr_info("CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n", in store_cpu_topology()
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H A Ddevtree.c61 * and builds the cpu logical map array containing MPIDR values related to
71 * contain a list of MPIDR[23:0] values where MPIDR[31:24] must in arm_dt_init_cpu_maps()
77 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; in arm_dt_init_cpu_maps() local
93 * defines the MPIDR[23:0]. in arm_dt_init_cpu_maps()
105 * to avoid matching valid MPIDR[23:0] values. in arm_dt_init_cpu_maps()
115 * Build a stashed array of MPIDR values. Numbering scheme in arm_dt_init_cpu_maps()
119 * boot CPU MPIDR is detected, this is recorded so that the in arm_dt_init_cpu_maps()
123 if (hwid == mpidr) { in arm_dt_init_cpu_maps()
152 pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n"); in arm_dt_init_cpu_maps()
/openbmc/linux/arch/arm64/kernel/
H A Dsleep.S18 * @mpidr: register containing MPIDR_EL1 value
19 * @mask: register containing MPIDR mask
25 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
27 * u64 mpidr_masked = mpidr & mask;
34 * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
37 (eg: a macro instance with mpidr = x1 and dst = x1 is invalid)
39 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
40 and \mpidr, \mpidr, \mask // mask out MPIDR bits
41 and \dst, \mpidr, #0xff // mask=aff0
43 and \mask, \mpidr, #0xff00 // mask = aff1
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H A Dsmp.c197 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; in secondary_start_kernel() local
253 cpu, (unsigned long)mpidr, in secondary_start_kernel()
470 * matching valid MPIDR values.
526 pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); in acpi_map_gic_cpu_interface()
531 pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); in acpi_map_gic_cpu_interface()
536 pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); in acpi_map_gic_cpu_interface()
543 pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n", in acpi_map_gic_cpu_interface()
555 /* map the logical cpu id to cpu MPIDR */ in acpi_map_gic_cpu_interface()
622 * cpu logical map array containing MPIDR values related to logical
680 * cpu logical map array containing MPIDR values related to logical
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/openbmc/linux/arch/arm/mach-milbeaut/
H A Dplatsmp.c25 unsigned int mpidr, cpu, cluster; in m10v_boot_secondary() local
30 mpidr = cpu_logical_map(l_cpu); in m10v_boot_secondary()
31 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in m10v_boot_secondary()
32 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in m10v_boot_secondary()
48 unsigned int mpidr, cpu, cluster; in m10v_smp_init() local
59 mpidr = read_cpuid_mpidr(); in m10v_smp_init()
60 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in m10v_smp_init()
61 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in m10v_smp_init()
78 unsigned int mpidr, cpu; in m10v_cpu_kill() local
80 mpidr = cpu_logical_map(l_cpu); in m10v_cpu_kill()
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/openbmc/linux/arch/arm/common/
H A Dmcpm_platsmp.c22 unsigned int mpidr; in cpu_to_pcpu() local
24 mpidr = cpu_logical_map(cpu); in cpu_to_pcpu()
25 *pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in cpu_to_pcpu()
26 *pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in cpu_to_pcpu()
73 unsigned int mpidr, pcpu, pcluster; in mcpm_cpu_die() local
74 mpidr = read_cpuid_mpidr(); in mcpm_cpu_die()
75 pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_die()
76 pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in mcpm_cpu_die()
H A Dmcpm_entry.c241 unsigned int mpidr, cpu, cluster; in mcpm_cpu_power_down() local
245 mpidr = read_cpuid_mpidr(); in mcpm_cpu_power_down()
246 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_power_down()
247 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in mcpm_cpu_power_down()
330 unsigned int mpidr = read_cpuid_mpidr(); in mcpm_cpu_suspend() local
331 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_suspend()
332 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in mcpm_cpu_suspend()
342 unsigned int mpidr, cpu, cluster; in mcpm_cpu_powered_up() local
349 mpidr = read_cpuid_mpidr(); in mcpm_cpu_powered_up()
350 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_powered_up()
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H A DbL_switcher.c46 * Use our own MPIDR accessors as the generic ones in asm/cputype.h have
124 unsigned int mpidr = read_mpidr(); in bL_switchpoint() local
125 unsigned int clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1); in bL_switchpoint()
149 unsigned int mpidr, this_cpu, that_cpu; in bL_switch_to() local
169 pr_debug("before switch: CPU %d MPIDR %#x -> %#x\n", in bL_switch_to()
236 mpidr = read_mpidr(); in bL_switch_to()
237 pr_debug("after switch: CPU %d MPIDR %#x\n", this_cpu, mpidr); in bL_switch_to()
238 BUG_ON(mpidr != ib_mpidr); in bL_switch_to()
515 int bL_switcher_get_logical_index(u32 mpidr) in bL_switcher_get_logical_index() argument
522 mpidr &= MPIDR_HWID_BITMASK; in bL_switcher_get_logical_index()
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/openbmc/linux/arch/arm/mach-hisi/
H A Dplatmcpm.c100 unsigned int mpidr, cpu, cluster; in hip04_boot_secondary() local
104 mpidr = cpu_logical_map(l_cpu); in hip04_boot_secondary()
105 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in hip04_boot_secondary()
106 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in hip04_boot_secondary()
155 unsigned int mpidr, cpu, cluster; in hip04_cpu_die() local
158 mpidr = cpu_logical_map(l_cpu); in hip04_cpu_die()
159 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in hip04_cpu_die()
160 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in hip04_cpu_die()
193 unsigned int mpidr, cpu, cluster; in hip04_cpu_kill() local
196 mpidr = cpu_logical_map(l_cpu); in hip04_cpu_kill()
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/openbmc/linux/arch/arm64/include/asm/
H A Dsmp_plat.h30 * Retrieve logical cpu index corresponding to a given MPIDR.Aff*
31 * - mpidr: MPIDR.Aff* bits to be used for the look-up
35 static inline int get_logical_index(u64 mpidr) in get_logical_index() argument
39 if (cpu_logical_map(cpu) == mpidr) in get_logical_index()
/openbmc/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst83 values: | mpidr | offset |
93 specified by the mpidr.
104 The mpidr field is used to specify which
105 redistributor is accessed. The mpidr is ignored for the distributor.
107 The mpidr encoding is based on the affinity information in the
108 architecture defined MPIDR, and the field is encoded as follows::
114 regardless of the mpidr used to access the register.
177 values: | mpidr | RES | instr |
179 The mpidr field encodes the CPU ID based on the affinity information in the
180 architecture defined MPIDR, and the field is encoded as follows::
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/openbmc/linux/drivers/bus/
H A Darm-cci.c117 u64 mpidr; member
132 static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr) in init_cpu_port() argument
135 port->mpidr = mpidr; in init_cpu_port()
143 static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr) in cpu_port_match() argument
145 return port->mpidr == (mpidr & MPIDR_HWID_BITMASK); in cpu_port_match()
254 * @mpidr: mpidr of the CPU whose CCI port should be disabled
265 int notrace cci_disable_port_by_cpu(u64 mpidr) in cci_disable_port_by_cpu() argument
271 if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) { in cci_disable_port_by_cpu()
302 " mrc p15, 0, r0, c0, c0, 5 @ get MPIDR value \n" in cci_enable_port_for_self()
309 /* Loop over the cpu_port array looking for a matching MPIDR */ in cci_enable_port_for_self()
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/openbmc/linux/arch/arm/include/asm/
H A Dsmp_plat.h75 * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
76 * - mpidr: MPIDR[23:0] to be used for the look-up
80 static inline int get_logical_index(u32 mpidr) in get_logical_index() argument
84 if (cpu_logical_map(cpu) == mpidr) in get_logical_index()
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S454 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
455 * MPIDR[7:2] = AFF0_RES
456 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
457 * MPIDR[23:16] = AFF2_CLUSTERID
458 * MPIDR[24] = MT
459 * MPIDR[29:25] = RES0
460 * MPIDR[30] = U
461 * MPIDR[31] = ME
462 * MPIDR[39:32] = AFF3
468 * LPID = MPIDR[15:8] | MPIDR[1:0]
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/openbmc/linux/arch/arm64/kvm/hyp/nvhe/
H A Dpsci-relay.c78 static unsigned int find_cpu_id(u64 mpidr) in find_cpu_id() argument
83 if (mpidr & ~MPIDR_HWID_BITMASK) in find_cpu_id()
87 if (cpu_logical_map(i) == mpidr) in find_cpu_id()
109 DECLARE_REG(u64, mpidr, host_ctxt, 1); in psci_cpu_on()
119 * Find the logical CPU ID for the given MPIDR. The search set is in psci_cpu_on()
125 cpu_id = find_cpu_id(mpidr); in psci_cpu_on()
140 ret = psci_call(func_id, mpidr, in psci_cpu_on()
/openbmc/linux/arch/arm/mach-shmobile/
H A Dheadsmp.S48 mrc p15, 0, r0, c0, c0, 5 @ r0 = MPIDR
93 * Per-CPU SMP boot function/argument selection code based on MPIDR
97 mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR
103 add r5, r5, r2 @ array of per-cpu mpidr values
/openbmc/linux/arch/arm/mach-sunxi/
H A Dmc_smp.c393 unsigned int mpidr, cpu, cluster; in sunxi_mc_smp_boot_secondary() local
395 mpidr = cpu_logical_map(l_cpu); in sunxi_mc_smp_boot_secondary()
396 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in sunxi_mc_smp_boot_secondary()
397 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in sunxi_mc_smp_boot_secondary()
445 unsigned int mpidr, cpu, cluster; in sunxi_mc_smp_cpu_die() local
448 mpidr = cpu_logical_map(l_cpu); in sunxi_mc_smp_cpu_die()
449 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in sunxi_mc_smp_cpu_die()
450 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in sunxi_mc_smp_cpu_die()
535 unsigned int mpidr, cpu, cluster; in sunxi_mc_smp_cpu_kill() local
540 mpidr = cpu_logical_map(l_cpu); in sunxi_mc_smp_cpu_kill()
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/openbmc/qemu/target/arm/tcg/
H A Dpsci.c69 uint64_t context_id, mpidr; in arm_handle_psci_call() local
100 mpidr = param[1]; in arm_handle_psci_call()
104 target_cpu_state = arm_get_cpu_by_id(mpidr); in arm_handle_psci_call()
148 mpidr = param[1]; in arm_handle_psci_call()
151 ret = arm_set_cpu_on(mpidr, entry, context_id, in arm_handle_psci_call()
/openbmc/linux/arch/arm/mach-exynos/
H A Dplatsmp.c51 u32 mpidr = cpu_logical_map(cpu); in platform_do_lowpower() local
52 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in platform_do_lowpower()
320 u32 mpidr = cpu_logical_map(cpu); in exynos_boot_secondary() local
321 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in exynos_boot_secondary()
425 u32 mpidr = cpu_logical_map(cpu); in exynos_cpu_die() local
426 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in exynos_cpu_die()
/openbmc/linux/drivers/cpufreq/
H A Dtegra194-cpufreq.c99 static void tegra_get_cpu_mpidr(void *mpidr) in tegra_get_cpu_mpidr() argument
101 *((u64 *)mpidr) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; in tegra_get_cpu_mpidr()
106 u64 mpidr; in tegra234_get_cpu_cluster_id() local
108 smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true); in tegra234_get_cpu_cluster_id()
111 *cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 1); in tegra234_get_cpu_cluster_id()
113 *clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 2); in tegra234_get_cpu_cluster_id()
198 u64 mpidr; in tegra194_get_cpu_cluster_id() local
200 smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true); in tegra194_get_cpu_cluster_id()
203 *cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 0); in tegra194_get_cpu_cluster_id()
205 *clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1); in tegra194_get_cpu_cluster_id()
/openbmc/linux/drivers/irqchip/
H A Dirq-gic-v3.c134 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4) argument
704 u64 mpidr = cpu_logical_map(cpu); in gic_cpu_to_affinity() local
709 mpidr = (MPIDR_AFFINITY_LEVEL(mpidr, 1) | in gic_cpu_to_affinity()
710 (MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8)); in gic_cpu_to_affinity()
712 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | in gic_cpu_to_affinity()
713 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | in gic_cpu_to_affinity()
714 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | in gic_cpu_to_affinity()
715 MPIDR_AFFINITY_LEVEL(mpidr, 0)); in gic_cpu_to_affinity()
1015 unsigned long mpidr; in __gic_populate_rdist() local
1023 mpidr = gic_cpu_to_affinity(smp_processor_id()); in __gic_populate_rdist()
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A Dspc.c98 * It corresponds to A15 processors MPIDR[15:8] bitfield
142 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
143 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
175 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
176 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
197 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
225 * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
226 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
/openbmc/linux/include/linux/
H A Darm-cci.h26 extern int cci_disable_port_by_cpu(u64 mpidr);
34 static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; } in cci_disable_port_by_cpu() argument
/openbmc/linux/include/ras/
H A Dras_event.h178 __field(u64, mpidr)
191 __entry->mpidr = proc->mpidr;
193 __entry->mpidr = 0ULL;
204 TP_printk("affinity level: %d; MPIDR: %016llx; MIDR: %016llx; "
206 __entry->affinity, __entry->mpidr, __entry->midr,

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