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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dloongson,liointc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson Local I/O Interrupt Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips and
14 Loongson-2K1000 chip, as the primary package interrupt controller which
18 - $ref: /schemas/interrupt-controller.yaml#
23 - loongson,liointc-1.0
[all …]
H A Dloongson,eiointc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,eiointc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson Extended I/O Interrupt Controller
10 - Binbin Zhou <zhoubinbin@loongson.cn>
13 This interrupt controller is found on the Loongson-3 family chips and
14 Loongson-2K series chips and is used to distribute interrupts directly to
18 - $ref: /schemas/interrupt-controller.yaml#
23 - loongson,ls2k0500-eiointc
[all …]
H A Dloongson,htvec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-3 HyperTransport Interrupt Vector Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips for
18 const: loongson,htvec-1.0
28 interrupt-controller: true
30 '#interrupt-cells':
[all …]
H A Dloongson,htpic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-3 HyperTransport Interrupt Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 This interrupt controller is found in the Loongson-3 family of chips to transmit
21 const: loongson,htpic-1.0
32 interrupt-controller: true
[all …]
/openbmc/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
27 +-----+ +---------+ +-------+
[all …]
H A Dintroduction.rst1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
40 ``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No
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/openbmc/linux/drivers/platform/mips/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 MIPS platforms, including vendor-specific netbook/laptop/desktop
21 bool "Loongson-3 CPU HWMon Driver"
26 Loongson-3A/3B CPU Hwmon (temperature sensor) driver.
29 bool "Loongson RS780E ACPI Controller"
32 Loongson RS780E PCH ACPI Controller driver.
35 bool "Loongson-2K1000 Reset Controller"
38 Loongson-2K1000 Reset Controller driver.
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dloongson.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/loongson.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCI Host Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 PCI host controller found on Loongson PCHs and SoCs.
16 - $ref: /schemas/pci/pci-bus.yaml#
21 - loongson,ls2k-pci
22 - loongson,ls7a-pci
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/openbmc/qemu/docs/system/
H A Dcpu-models-mips.rst.inc16 ``mips32r6-generic``
51 ``Loongson-2E``
52 MIPS64 Processor (Loongson 2, 2006)
54 ``Loongson-2F``
55 MIPS64 Processor (Loongson 2, 2008)
57 ``Loongson-3A1000``
58 MIPS64 Processor (Loongson 3, 2010)
60 ``Loongson-3A4000``
61 MIPS64 Processor (Loongson 3, 2018)
66 ``MIPS64R2-generic``, ``5KEc``, ``5KEf``
/openbmc/linux/arch/mips/include/asm/mach-loongson64/
H A Dkernel-entry-init.h7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
28 /* Loongson-3A R4+ */
33 /* Loongson-3A R2/R3 */
59 /* Loongson-3A R4+ */
64 /* Loongson-3A R2/R3 */
91 b 2f /* Loongson-3A1000/3A2000/3A3000/3A4000 */
92 1: dins a0, t2, 14, 2 /* Loongson-3B1000/3B1500 need bit 15~14 */
94 3: addiu t9, -1 /* limit mailbox access */
95 bnez t9, 3b
H A Dloongson.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
20 /* machine-specific boot configuration */
40 /* machine-specific reboot/halt operation */
49 /* loongson-specific command line, env and memory initialization */
77 #define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
81 #define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
85 #define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
88 #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
89 /* Loongson-3 specific registers */
92 #define LOONGSON3_REG_TOP (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
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/openbmc/smbios-mdr/include/
H A Dcpu.hpp8 // http://www.apache.org/licenses/LICENSE-2.0
77 {0x1b, "K6-2"},
78 {0x1c, "K6-3"},
81 {0x1f, "K6-2+"},
106 {0x38, "AMD Turion II Ultra Dual-Core Mobile M Processor Family"},
107 {0x39, "AMD Turion II Dual-Core Mobile M Processor Family"},
108 {0x3a, "AMD Athlon II Dual-Core M Processor Family"},
120 {0x46, "AMD C-Series Processor"},
121 {0x47, "AMD E-Series Processor"},
122 {0x48, "AMD A-Series Processor"},
[all …]
/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
6 :Translator: Huacai Chen <chenhuacai@loongson.cn>
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
[all …]
H A Dintroduction.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
6 :Translator: Huacai Chen <chenhuacai@loongson.cn>
12 LoongArch是一种新的RISC ISA，在一定程度上类似于MIPS和RISC-V。LoongArch指令集
25 ----------
32 :ref:`参考文献 <loongarch-references-zh_CN>`:
41 ``$r4``-``$r11`` ``$a0``-``$a7`` 参数寄存器 否
42 ``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否
43 ``$r12``-``$r20`` ``$t0``-``$t8`` 临时寄存器 否
46 ``$r23``-``$r31`` ``$s0``-``$s8`` 静态寄存器 是
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/openbmc/linux/arch/mips/boot/dts/loongson/
H A Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
8 compatible = "loongson,loongson2k1000";
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "loongson,gs264";
21 #clock-cells = <1>;
[all …]
/openbmc/qemu/target/loongarch/
H A DREADME1 - Introduction
3 LoongArch is the general processor architecture of Loongson.
6 core: 3A5000
7 …https://github.com/loongson/LoongArch-Documentation/releases/download/2021.08.17/LoongArch-Vol1-v1…
9 …We can get the latest loongarch documents at https://github.com/loongson/LoongArch-Documentation/t…
12 - System emulation
16 - Linux-user emulation
18 …We already support Linux user emulation. We can use LoongArch cross-tools to build LoongArch execu…
19 and We can also use qemu-loongarch64 to run LoongArch executables.
21 1. Config cross-tools env.
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/openbmc/linux/drivers/irqchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
121 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
129 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
211 bool "J-Core integrated AIC" if COMPILE_TEST
215 Support for the J-Core integrated AIC.
226 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
229 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
234 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
284 tristate "TS-4800 IRQ controller"
289 Support for the TS-4800 FPGA IRQ controller
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/openbmc/linux/arch/loongarch/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
214 # MIPS Loongson code, to preserve Loongson-specific code paths in drivers that
246 default 3 if PGTABLE_3LEVEL
254 def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x))
257 def_bool $(as-instr,movfcsr2gr \$t0$(comma)\$fcsr0)
260 def_bool $(as-instr,vld \$vr0$(comma)\$a0$(comma)0)
263 def_bool $(as-instr,xvld \$xr0$(comma)\$a0$(comma)0)
266 def_bool $(as-instr,movscr2gr \$a0$(comma)\$scr0)
282 bool "4KB with 3 levels"
286 This option selects 4KB page size with 3 level page tables, which
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/openbmc/linux/Documentation/devicetree/bindings/mips/loongson/
H A Drs780e-acpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mips/loongson/rs780e-acpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson RS780E PCH ACPI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This controller can be found in Loongson-3 systems with RS780E PCH.
17 const: loongson,rs780e-acpi
23 - compatible
24 - reg
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-loongson.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Loongson-2F/3A/3B GPIO Support
6 * Copyright (c) 2008-2010 Arnaud Patard <apatard@mandriva.com>
20 #include <loongson.h>
97 struct device *dev = &pdev->dev; in loongson_gpio_probe()
101 return -ENOMEM; in loongson_gpio_probe()
103 gc->label = "loongson-gpio-chip"; in loongson_gpio_probe()
104 gc->base = 0; in loongson_gpio_probe()
105 gc->ngpio = LOONGSON_N_GPIO; in loongson_gpio_probe()
106 gc->get = loongson_gpio_get_value; in loongson_gpio_probe()
[all …]
/openbmc/linux/arch/mips/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
135 bool "Generic board-agnostic MIPS kernel"
224 Support for the Texas Instruments AR7 System-on-a-Chip
298 Build a generic DT-based kernel image that boots on select
299 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
391 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
392 DECstation porting pages on <http://decstation.unix-ag.org/>.
432 Olivetti M700-10 workstations.
468 bool "Loongson 32-bit family of machines"
471 This enables support for the Loongson-1 family of machines.
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/openbmc/qemu/hw/mips/
H A Dloongson3_virt.c2 * Generic Loongson-3 Platform support
4 * Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com)
5 * Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
22 * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
32 #include "hw/char/serial-mm.h"
45 #include "hw/pci-host/gpex.h"
52 #include "qemu/error-report.h"
59 * Loongson-3's virtual machine BIOS can be obtained here:
60 * 1, https://github.com/loongson-community/firmware-nonfree
104 #define TYPE_LOONGSON_MACHINE MACHINE_TYPE_NAME("loongson3-virt")
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/openbmc/linux/drivers/pci/controller/
H A Dpci-loongson.c1 // SPDX-License-Identifier: GPL-2.0
3 * Loongson PCI Host Controller Driver
12 #include <linux/pci-acpi.h>
13 #include <linux/pci-ecam.h>
41 #define FLAG_DEV_HIDDEN BIT(3)
58 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in bridge_class_quirk()
73 pdev->mmio_always_on = 1; in system_bus_quirk()
74 pdev->non_compliant_bars = 1; in system_bus_quirk()
84 * Some Loongson PCIe ports have hardware limitations on their Maximum Read
87 * bridges. However, some MIPS Loongson firmware doesn't set MRRS properly,
[all …]
/openbmc/linux/arch/loongarch/include/asm/
H A Dcpu.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
12 * As described in LoongArch specs from Loongson Technology, the PRID register
15 * +---------------+----------------+------------+--------------------+
17 * +---------------+----------------+------------+--------------------+
37 #define PRID_SERIES_LA132 0x8000 /* Loongson 32bit */
38 #define PRID_SERIES_LA264 0xa000 /* Loongson 64bit, 2-issue */
39 #define PRID_SERIES_LA364 0xb000 /* Loongson 64bit, 3-issue */
40 #define PRID_SERIES_LA464 0xc000 /* Loongson 64bit, 4-issue */
41 #define PRID_SERIES_LA664 0xd000 /* Loongson 64bit, 6-issue */
[all …]
/openbmc/linux/tools/perf/arch/loongarch/entry/syscalls/
H A Dmksyscalltbl2 # SPDX-License-Identifier: GPL-2.0
7 # Author(s): Ming Wang <wangming01@loongson.cn>
8 # Author(s): Huacai Chen <chenhuacai@loongson.cn>
9 # Copyright (C) 2020-2023 Loongson Technology Corporation Limited
13 incpath=$3
16 if ! test -r $input; then
41 $gcc -E -dM -x c -I $incpath/include/uapi $input \
42 |awk '$2 ~ "__NR" && $3 !~ "__NR3264_" {
44 print | "sort -k2 -n"}' \

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