| /openbmc/linux/Documentation/devicetree/bindings/mips/loongson/ |
| H A D | devices.yaml | 20 - description: Classic Loongson64 Quad Core + LS7A
22 - const: loongson,loongson64c-4core-ls7a
32 - description: Generic Loongson64 Quad Core + LS7A
34 - const: loongson,loongson64g-4core-ls7a
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| /openbmc/linux/arch/mips/boot/dts/loongson/ |
| H A D | loongson64c_4core_ls7a.dts | 6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
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| H A D | loongson64g_4core_ls7a.dts | 6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
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| H A D | ls7a-pch.dtsi | 23 compatible = "loongson,ls7a-rtc";
69 compatible = "loongson,ls7a-pci";
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| /openbmc/linux/Documentation/devicetree/bindings/rtc/ |
| H A D | loongson,rtc.yaml | 25 - loongson,ls7a-rtc
31 - const: loongson,ls7a-rtc
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| /openbmc/linux/arch/mips/loongson64/ |
| H A D | env.c | 186 pr_info("The bridge chip is LS7A\n"); in prom_lefi_init_env()
187 loongson_sysconf.bridgetype = LS7A; in prom_lefi_init_env()
212 case LS7A: in prom_lefi_init_env()
233 if (loongson_sysconf.bridgetype == LS7A) in prom_lefi_init_env()
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| /openbmc/linux/Documentation/arch/loongarch/ |
| H A D | irq-chip-model.rst | 8 with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
142 Documentation of Loongson's LS7A chipset:
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| /openbmc/qemu/docs/system/loongarch/ |
| H A D | virt.rst | 16 - Ls7a RTC device
17 - Ls7a IOAPIC device
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| /openbmc/linux/drivers/gpu/drm/loongson/ |
| H A D | Kconfig | 12 LS7A2000, LS7A1000, LS2K2000 and LS2K1000 etc. Loongson LS7A
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| /openbmc/linux/drivers/i2c/busses/ |
| H A D | i2c-ls2x.c | 3 * Loongson-2K/Loongson LS7A I2C master mode driver
346 { .compatible = "loongson,ls7a-i2c" },
352 { "LOON0004" }, /* Loongson LS7A */
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| /openbmc/linux/Documentation/devicetree/bindings/i2c/ |
| H A D | loongson,ls2x-i2c.yaml | 19 - loongson,ls7a-i2c
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | loongson,pch-pic.yaml | 13 This interrupt controller is found in the Loongson LS7A family of PCH for
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| H A D | loongson,pch-msi.yaml | 13 This interrupt controller is found in the Loongson LS7A family of PCH for
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | loongson.yaml | 22 - loongson,ls7a-pci
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | loongson,ls-gpio.yaml | 16 - loongson,ls7a-gpio
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| /openbmc/linux/drivers/pci/controller/ |
| H A D | pci-loongson.c | 278 /* LS2K/LS7A accept 8/16/32-bit PCI config operations */
310 { .compatible = "loongson,ls7a-pci",
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| /openbmc/qemu/hw/rtc/ |
| H A D | ls7a_rtc.c | 3 * LoongArch LS7A Real Time Clock emulation
473 dc->desc = "ls7a rtc"; in ls7a_rtc_class_init()
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| /openbmc/linux/arch/loongarch/include/asm/ |
| H A D | loongson.h | 63 /* ============== LS7A registers =============== */
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| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-loongson-64bit.c | 206 .compatible = "loongson,ls7a-gpio",
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| /openbmc/linux/arch/mips/include/asm/mach-loongson64/ |
| H A D | boot_param.h | 203 LS7A = 1, enumerator
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | snps,dwmac.yaml | 68 - loongson,ls7a-dwmac
641 - loongson,ls7a-dwmac
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| /openbmc/qemu/hw/intc/ |
| H A D | loongarch_pch_pic.c | 12 #include "hw/pci-host/ls7a.h"
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| /openbmc/linux/arch/loongarch/ |
| H A D | Kconfig | 485 with LS7A chipsets the WUC attribute (Weak-ordered UnCached, which
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| /openbmc/linux/drivers/rtc/ |
| H A D | rtc-loongson.c | 370 { .compatible = "loongson,ls7a-rtc", .data = &generic_rtc_config },
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| /openbmc/qemu/hw/loongarch/ |
| H A D | virt.c | 30 #include "hw/pci-host/ls7a.h"
274 "loongson,ls7a-rtc"); in fdt_add_rtc_node()
|