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/openbmc/linux/drivers/isdn/mISDN/
H A Dlayer1.c94 struct layer1 *l1 = fi->userdata; in l1m_debug() local
103 printk(KERN_DEBUG "%s: %pV\n", dev_name(&l1->dch->dev.dev), &vaf); in l1m_debug()
117 struct layer1 *l1 = fi->userdata; in l1_deact_cnf() local
120 if (test_bit(FLG_L1_ACTIVATING, &l1->Flags)) in l1_deact_cnf()
121 l1->dcb(l1->dch, HW_POWERUP_REQ); in l1_deact_cnf()
127 struct layer1 *l1 = fi->userdata; in l1_deact_req_s() local
130 mISDN_FsmRestartTimer(&l1->timerX, 550, EV_TIMER_DEACT, NULL, 2); in l1_deact_req_s()
131 test_and_set_bit(FLG_L1_DEACTTIMER, &l1->Flags); in l1_deact_req_s()
137 struct layer1 *l1 = fi->userdata; in l1_power_up_s() local
139 if (test_bit(FLG_L1_ACTIVATING, &l1->Flags)) { in l1_power_up_s()
[all …]
/openbmc/qemu/tests/unit/
H A Dtest-hbitmap.c19 #define L1 BITS_PER_LONG macro
20 #define L2 (BITS_PER_LONG * L1)
233 hbitmap_test_init(data, L1, 0); in test_hbitmap_iter_empty()
242 hbitmap_test_check(data, L1 - 1); in test_hbitmap_iter_partial()
243 hbitmap_test_check(data, L1); in test_hbitmap_iter_partial()
244 hbitmap_test_check(data, L1 * 2 - 1); in test_hbitmap_iter_partial()
248 hbitmap_test_check(data, L2 + L1); in test_hbitmap_iter_partial()
249 hbitmap_test_check(data, L2 + L1 * 2 - 1); in test_hbitmap_iter_partial()
253 hbitmap_test_check(data, L2 * 2 + L1); in test_hbitmap_iter_partial()
254 hbitmap_test_check(data, L2 * 2 + L1 * 2 - 1); in test_hbitmap_iter_partial()
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/openbmc/linux/Documentation/networking/
H A Dtls-offload-layers.svg1 …l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.82812…
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A Dmemory.json40 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
46 …"BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 1…
52 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
58 "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
64 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pa…
70 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coale…
76 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pa…
82 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pa…
88 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all p…
94 "BriefDescription": "L1 DTLB misses for all page sizes.",
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H A Drecommended.json23 "BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).",
29 "BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).",
47 "BriefDescription": "L2 cache misses from L1 instruction cache misses.",
53 "BriefDescription": "L2 cache misses from L1 data cache misses.",
71 "BriefDescription": "L2 cache hits from L1 instruction cache misses.",
77 "BriefDescription": "L2 cache hits from L1 data cache misses.",
120 "BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node.",
126 "BriefDescription": "L1 data cache fills from a different NUMA node.",
132 "BriefDescription": "L1 data cache fills from within the same CCX.",
138 "BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node.",
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/openbmc/qemu/target/i386/
H A Dmonitor.c74 unsigned int l1, l2; in tlb_info_32() local
78 for(l1 = 0; l1 < 1024; l1++) { in tlb_info_32()
79 cpu_physical_memory_read(pgd + l1 * 4, &pde, 4); in tlb_info_32()
84 print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1)); in tlb_info_32()
90 print_pte(mon, env, (l1 << 22) + (l2 << 12), in tlb_info_32()
102 unsigned int l1, l2, l3; in tlb_info_pae32() local
107 for (l1 = 0; l1 < 4; l1++) { in tlb_info_pae32()
108 cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8); in tlb_info_pae32()
118 print_pte(mon, env, (l1 << 30) + (l2 << 21), pde, in tlb_info_pae32()
126 print_pte(mon, env, (l1 << 30) + (l2 << 21) in tlb_info_pae32()
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/openbmc/linux/security/selinux/ss/
H A Dmls_types.h30 static inline int mls_level_eq(const struct mls_level *l1, const struct mls_level *l2) in mls_level_eq() argument
32 return ((l1->sens == l2->sens) && in mls_level_eq()
33 ebitmap_cmp(&l1->cat, &l2->cat)); in mls_level_eq()
36 static inline int mls_level_dom(const struct mls_level *l1, const struct mls_level *l2) in mls_level_dom() argument
38 return ((l1->sens >= l2->sens) && in mls_level_dom()
39 ebitmap_contains(&l1->cat, &l2->cat, 0)); in mls_level_dom()
42 #define mls_level_incomp(l1, l2) \ argument
43 (!mls_level_dom((l1), (l2)) && !mls_level_dom((l2), (l1)))
45 #define mls_level_between(l1, l2, l3) \ argument
46 (mls_level_dom((l1), (l2)) && mls_level_dom((l3), (l1)))
/openbmc/qemu/tests/qemu-iotests/
H A D080.out40 == Invalid L1 table ==
42 qemu-io: can't open device TEST_DIR/t.qcow2: Active L1 table too large
43 qemu-io: can't open device TEST_DIR/t.qcow2: Active L1 table too large
44 qemu-io: can't open device TEST_DIR/t.qcow2: Active L1 table offset invalid
45 qemu-io: can't open device TEST_DIR/t.qcow2: Active L1 table offset invalid
47 == Invalid L1 table (with internal snapshot in the image) ==
49 qemu-img: Could not open 'TEST_DIR/t.IMGFMT': L1 table is too small
62 == Invalid snapshot L1 table offset ==
66 qemu-img: Failed to load snapshot: Snapshot L1 table offset invalid
67 qemu-img: Snapshot L1 table offset invalid
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/openbmc/linux/arch/sparc/kernel/
H A Drtrap_64.S62 andn %l1, %o0, %l1
85 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
87 and %l1, %l4, %l4
88 andn %l1, %l4, %l1
96 rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
98 and %l1, %l4, %l4
99 andn %l1, %l4, %l1
115 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
118 and %l1, %l4, %l4
119 andn %l1, %l4, %l1
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H A Dhead_64.S169 mov (1b - prom_peer_name), %l1
170 sub %l0, %l1, %l1
174 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
184 mov (1b - prom_root_node), %l1
185 sub %l0, %l1, %l1
186 stw %l4, [%l1]
188 mov (1b - prom_getprop_name), %l1
191 sub %l0, %l1, %l1
198 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
212 mov (1b - prom_finddev_name), %l1
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/
H A Dcache.json7 …"PublicDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This…
11 …ess which causes data to be read from outside the L1, including accesses which do not allocate int…
15 …ny load or store operation or page table walk access which looks up in the L1 data cache. In parti…
19 …"PublicDescription": "This event counts any refill of the data L1 TLB from the L2 TLB. This includ…
23 …p cache access. This event counts any instruction fetch which accesses the L1 instruction cache or…
27 …"PublicDescription": "This event counts any write-back of data from the L1 data cache to L2 or L3.…
31 …n": "This event counts any transaction from L1 which looks up in the L2 cache, and any write-back …
35 …": "L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to…
39 …ch do not write data outside of the core and snoops which return data from the L1 are not counted",
43 …t cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate…
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/openbmc/linux/Documentation/virt/kvm/x86/
H A Drunning-nested-guests.rst19 | L1 (Guest Hypervisor) |
33 - L1 – level-1 guest; a VM running on L0; also called the "guest
36 - L2 – level-2 guest; a VM running on L1, this is the "nested guest"
45 metal, running the LPAR hypervisor), L1 (host hypervisor), L2
49 L1, and L2) for all architectures; and will largely focus on
148 able to start an L1 guest with::
175 2. The guest hypervisor (L1) must be provided with the ``sie`` CPU
179 3. Now the KVM module can be loaded in the L1 (guest hypervisor)::
187 Migrating an L1 guest, with a *live* nested guest in it, to another
191 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest
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/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A Drecommended.json12 "BriefDescription": "All L1 Data Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
124 "BriefDescription": "L1 Data Cache Fills: From Memory",
130 "BriefDescription": "L1 Data Cache Fills: From Remote Node",
136 "BriefDescription": "L1 Data Cache Fills: From within same CCX",
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H A Dbranch.json5 "BriefDescription": "L1 Branch Prediction Overrides Existing Prediction (speculative)."
27 "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.",
33 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB…
39 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instruction TLB…
45 …"BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. L1 Instrcution TLB…
/openbmc/linux/tools/testing/selftests/powerpc/pmu/event_code_tests/
H A Dgroup_constraint_cache_test.c13 /* All L1 D cache load references counted at finish, gated by reject */
15 /* Load Missed L1 */
17 /* Load Missed L1 */
23 * Monitor Mode Control Register 1 (MMCR1: 16-17) for l1 cache.
34 /* Init the events for the group contraint check for l1 cache select bits */ in group_constraint_cache()
40 /* Expected to fail as sibling event doesn't request same l1 cache select bits as leader */ in group_constraint_cache()
45 /* Init the event for the group contraint l1 cache select test */ in group_constraint_cache()
48 /* Expected to succeed as sibling event request same l1 cache select bits as leader */ in group_constraint_cache()
/openbmc/qemu/target/mips/tcg/
H A Dloong_translate.c32 TCGLabel *l1, *l2, *l3; in gen_lext_DIV_G() local
41 l1 = gen_new_label(); in gen_lext_DIV_G()
52 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); in gen_lext_DIV_G()
55 gen_set_label(l1); in gen_lext_DIV_G()
86 TCGLabel *l1, *l2; in gen_lext_DIVU_G() local
95 l1 = gen_new_label(); in gen_lext_DIVU_G()
105 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); in gen_lext_DIVU_G()
109 gen_set_label(l1); in gen_lext_DIVU_G()
133 TCGLabel *l1, *l2, *l3; in gen_lext_MOD_G() local
142 l1 = gen_new_label(); in gen_lext_MOD_G()
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/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Dmemory.json115 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the…
124 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the…
133 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
142 …n": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches an…
151 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
160 …clusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches an…
169 …tion": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that wer…
178 …tion": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that wer…
187 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.",
196 …are prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches an…
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dqcom,smd-rpm-regulator.yaml27 For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
30 For pm6125 s1, s2, s3, s4, s5, s6, s7, s8, l1, l2, l3, l5, l6, l7, l8, l9,
33 For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22,
36 For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob
38 For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
44 For pm8909, s1, s2, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
47 For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
50 For pm8941, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
54 For pm8950 and pm8953, s1, s2, s3, s4, s5, s6, s7, l1, l2, l3, l4, l5, l6,
58 For pm8994, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3,
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A Drecommended.json12 "BriefDescription": "All L1 Data Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
110 "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
117 "BriefDescription": "L1 ITLB Misses",
130 "BriefDescription": "L1 DTLB Misses",
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Drecommended.json12 "BriefDescription": "All L1 Data Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
48 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
54 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
72 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
78 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
110 "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
117 "BriefDescription": "L1 ITLB Misses",
130 "BriefDescription": "L1 DTLB Misses",
/openbmc/linux/arch/sparc/lib/
H A Dxor.S370 ldda [%i1 + 0x30] %asi, %l0 /* %l0/%l1 = src + 0x30 */
390 xor %l3, %l1, %l3
418 ldda [%l7 + 0x10] %asi, %l0 /* %l0/%l1 = src2 + 0x10 */
431 xor %l1, %i5, %l1
433 xor %o3, %l1, %o3
437 ldda [%l7 + 0x30] %asi, %l0 /* %l0/%l1 = src2 + 0x30 */
449 xor %l1, %i5, %l1
451 xor %o3, %l1, %o3
482 ldda [%i0 + 0x00] %asi, %l0 /* %l0/%l1 = dest + 0x00 */
490 xor %l1, %g3, %l1
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A Dcore-imp-def.json267 "PublicDescription": "Dispatch stall due to L1 instruction cache miss",
270 "BriefDescription": "Dispatch stall due to L1 instruction cache miss"
273 "PublicDescription": "Dispatch stall due to L1 instruction TLB miss",
276 "BriefDescription": "Dispatch stall due to L1 instruction TLB miss"
279 "PublicDescription": "Dispatch stall due to L1 data cache miss",
282 "BriefDescription": "Dispatch stall due to L1 data cache miss"
285 "PublicDescription": "Dispatch stall due to L1 data TLB miss",
288 "BriefDescription": "Dispatch stall due to L1 data TLB miss"
459 "PublicDescription": "L1 prefetcher, load prefetch requests generated",
462 "BriefDescription": "L1 prefetcher, load prefetch requests generated"
[all …]
/openbmc/linux/fs/ntfs3/
H A Dupcase.c36 int ntfs_cmp_names(const __le16 *s1, size_t l1, const __le16 *s2, size_t l2, in ntfs_cmp_names() argument
41 size_t len = min(l1, l2); in ntfs_cmp_names()
55 return l1 - l2; in ntfs_cmp_names()
65 diff2 = l1 - l2; in ntfs_cmp_names()
74 size_t l1 = uni1->len; in ntfs_cmp_names_cpu() local
76 size_t len = min(l1, l2); in ntfs_cmp_names_cpu()
92 return l1 - l2; in ntfs_cmp_names_cpu()
102 diff2 = l1 - l2; in ntfs_cmp_names_cpu()
/openbmc/linux/drivers/gpu/drm/stm/
H A Dltdc.c87 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
88 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
89 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
90 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
91 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */
92 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */
93 #define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */
94 #define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */
95 #define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */
96 #define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */
[all …]
/openbmc/linux/drivers/pci/pcie/
H A Daspm.c3 * Enable PCIe link L0s/L1 state and Clock Power Management
32 #define ASPM_STATE_L1 (4) /* L1 state */
33 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
34 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
35 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
36 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
94 * The L1 PM substate capability is only implemented in function 0 in a
114 /* Enable ASPM L0s/L1 */ in policy_to_aspm_state()
285 /* Convert L1 latency encoding to ns */
295 /* Convert L1 acceptable latency encoding to ns */
[all …]

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