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Searched full:jazelle (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/linux-user/
H A Duname.c53 * Jazelle support */ in cpu_to_uname_machine()
/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c141 * set the field to indicate Jazelle support within QEMU. in arm926_initfn()
143 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); in arm926_initfn()
183 * set the field to indicate Jazelle support within QEMU. in arm1026_initfn()
185 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); in arm1026_initfn()
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,vexpress-juno.yaml53 and Jazelle support in the Cortex A5 family. See ARM DUI 0541C.
/openbmc/linux/arch/arm/kernel/
H A Dprocess.c62 "ARM" , "Thumb" , "Jazelle", "ThumbEE"
/openbmc/qemu/include/hw/xen/interface/
H A Darch-arm.h346 #define PSR_JAZELLE (1<<24) /* Jazelle Mode */
/openbmc/qemu/target/arm/
H A Dgdbstub.c76 * Jazelle DBX extensions. in arm_cpu_gdb_write_register()
H A Dcpu-features.h63 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; in isar_feature_aa32_jazelle()
H A Dcpu.h2022 FIELD(ID_ISAR1, JAZELLE, 28, 4)
/openbmc/linux/arch/arm/mm/
H A DKconfig264 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
/openbmc/linux/arch/arm64/tools/
H A Dsysreg460 Enum 31:28 Jazelle