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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnxp,s32g2-siul2-pinctrl.yaml21 IMCR registers need to be revealed for kernel to configure pinmux.
33 A list of MSCR/IMCR register regions to be reserved.
37 - IMCR (Input Multiplexed Signal Configuration Register)
38 An IMCR register can configure the associated pin as function input
44 - description: IMCR registers group 0 in SIUL2_0
45 - description: IMCR registers group 1 in SIUL2_1
46 - description: IMCR registers group 2 in SIUL2_1
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dddr2_defs.h27 unsigned int imcr; /* 0xCC */ member
/openbmc/u-boot/board/freescale/s32v234evb/
H A Ds32v234evb.c59 /* set RXD - IMCR[200] - 200 */ in setup_iomux_uart()
/openbmc/linux/arch/x86/include/asm/
H A Dmpspec_def.h29 unsigned char feature2; /* Bit7 set for IMCR|PIC */
/openbmc/linux/arch/x86/kernel/
H A Ddevicetree.c168 pr_info("%s compatibility mode.\n", pic_mode ? "IMCR and PIC" : "Virtual Wire"); in dtb_lapic_setup()
H A Dmpparse.c506 pr_info(" IMCR and PIC compatibility mode.\n"); in default_get_smp_config()
/openbmc/u-boot/arch/x86/include/asm/
H A Dmpspec.h27 u8 mpf_feature2; /* Bit7 set for IMCR/PIC */
/openbmc/linux/drivers/pinctrl/nxp/
H A Dpinctrl-s32g2.c718 /* IMCR pin ID ranges */
/openbmc/linux/arch/x86/kernel/apic/
H A Dapic.c124 * Handle interrupt mode configuration register (IMCR).
129 * PIC Mode by changing the IMCR.
2252 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's in connect_bsp_APIC()