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/openbmc/u-boot/include/dt-bindings/clock/
H A Drk3036-cru.h83 #define HCLK_NANDC 453 macro
H A Drk3128-cru.h86 #define HCLK_NANDC 453 macro
H A Drk3228-cru.h93 #define HCLK_NANDC 453 macro
H A Drv1108-cru.h145 #define HCLK_NANDC 323 macro
H A Drk3328-cru.h175 #define HCLK_NANDC 416 macro
/openbmc/linux/include/dt-bindings/clock/
H A Drk3036-cru.h83 #define HCLK_NANDC 453 macro
H A Drk3228-cru.h125 #define HCLK_NANDC 453 macro
H A Drk3128-cru.h127 #define HCLK_NANDC 453 macro
H A Drv1108-cru.h142 #define HCLK_NANDC 323 macro
H A Dpx30-cru.h130 #define HCLK_NANDC 254 macro
H A Drk3308-cru.h147 #define HCLK_NANDC 153 macro
H A Drk3328-cru.h178 #define HCLK_NANDC 316 macro
H A Drockchip,rv1126-cru.h297 #define HCLK_NANDC 233 macro
H A Drk3568-cru.h179 #define HCLK_NANDC 116 macro
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Drockchip,nand-controller.yaml140 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3036.c400 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
H A Dclk-rk3128.c495 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
H A Dclk-rk3228.c562 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
H A Dclk-rv1108.c737 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS),
H A Dclk-rv1126.c805 GATE(HCLK_NANDC, "hclk_nandc", "hclk_pdnvm", 0,
H A Dclk-rk3308.c820 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 6, GFLAGS),
H A Dclk-px30.c891 GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS),
/openbmc/u-boot/arch/arm/dts/
H A Drk3128.dtsi235 <&cru HCLK_NANDC>,
237 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi180 <&cru HCLK_NANDC>,
H A Drk3036.dtsi318 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;

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