| /openbmc/linux/Documentation/devicetree/bindings/iio/addac/ |
| H A D | adi,ad74115.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
23 compatible:
25 - adi,ad74115h
30 spi-max-frequency:
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| H A D | adi,ad74413r.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74412R and AD74413R are quad-channel software configurable input/output
18 The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide
20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
25 compatible:
27 - adi,ad74412r
28 - adi,ad74413r
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
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| H A D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
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| /openbmc/linux/Documentation/devicetree/bindings/riscv/ |
| H A D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
18 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some registers. This
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| H A D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
18 This document defines properties that indicate whether a hart supports a
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| /openbmc/u-boot/arch/riscv/lib/ |
| H A D | sifive_clint.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
6 * The CLINT block holds memory-mapped control and status registers
18 #define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4) argument
20 #define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) argument
30 if (!gd->arch.clint) { \
34 gd->arch.clint = ret; \
42 *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); in riscv_get_time()
47 int riscv_set_timecmp(int hart, u64 cmp) in riscv_set_timecmp() argument
51 writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); in riscv_set_timecmp()
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| /openbmc/linux/arch/riscv/kernel/ |
| H A D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
26 * Returns the hart ID of the given device tree node, or -ENODEV if the node
27 * isn't an enabled and valid RISC-V hart node.
29 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
33 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
34 if (*hart == ~0UL) { in riscv_of_processor_hartid()
35 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
36 return -ENODEV; in riscv_of_processor_hartid()
39 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
44 return -ENODEV; in riscv_of_processor_hartid()
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| /openbmc/u-boot/drivers/cpu/ |
| H A D | riscv_cpu.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <dm/device-internal.h>
21 return -ENOSPC; in riscv_cpu_get_desc()
32 dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); in riscv_cpu_get_info()
34 mmu = dev_read_string(dev, "mmu-type"); in riscv_cpu_get_info()
36 info->features |= BIT(CPU_FEAT_MMU); in riscv_cpu_get_info()
46 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { in riscv_cpu_get_count()
65 /* save the hart id */ in riscv_cpu_bind()
66 plat->cpu_id = dev_read_addr(dev); in riscv_cpu_bind()
68 ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); in riscv_cpu_bind()
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| /openbmc/linux/Documentation/devicetree/bindings/cpu/ |
| H A D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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| /openbmc/qemu/docs/system/riscv/ |
| H A D | microchip-icicle-kit.rst | 1 Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
5 SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
8 https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
11 https://www.microsemi.com/existing-parts/parts/152514
14 -----------------
16 The ``microchip-icicle-kit`` machine supports the following devices:
21 * Platform-Level Interrupt Controller (PLIC)
22 * L2 Loosely Integrated Memory (L2-LIM)
30 ------------
32 The ``microchip-icicle-kit`` machine can start using the standard -bios
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| H A D | virt.rst | 8 real-world hardware.
11 -----------------
17 * Platform-Level Interrupt Controller (PLIC)
19 * 1 NS16550 compatible UART
22 * 8 virtio-mmio transport devices
31 ----------------------------------
34 which it passes to the guest, if there is no ``-dtb`` option. This provides
39 If users want to provide their own DTB, they can use the ``-dtb`` option.
42 * The number of subnodes of the /cpus node should match QEMU's ``-smp`` option
43 * The /memory reg size should match QEMU’s selected ram_size via ``-m``
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| /openbmc/qemu/hw/riscv/ |
| H A D | sifive_u.c | 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
8 * Provides a board compatible with the SiFive Freedom U SDK:
15 * 5) OTP (One-Time Programmable) memory with stored serial number
39 #include "qemu/error-report.h"
99 uint64_t mem_size = ms->ram_size; in create_fdt()
111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()
114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()
121 qemu_fdt_setprop_string(fdt, "/", "compatible", in create_fdt()
122 "sifive,hifive-unleashed-a00"); in create_fdt()
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| H A D | virt-acpi-build.c | 4 * RISC-V virt ACPI generation
6 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
10 * Copyright (C) 2021-2023 Ventana Micro Systems Inc
27 #include "hw/acpi/acpi-defs.h"
29 #include "hw/acpi/aml-build.h"
34 #include "hw/pci-host/gpex.h"
37 #include "hw/virtio/virtio-acpi.h"
40 #include "qemu/error-report.h"
69 uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); in riscv_acpi_madt_add_rintc()
70 uint64_t hart_id = arch_ids->cpus[uid].arch_id; in riscv_acpi_madt_add_rintc()
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| H A D | microchip_pfsoc.c | 2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
9 * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
13 * 2) eNVM (Embedded Non-Volatile Memory)
14 * 3) MMUARTs (Multi-Mode UART)
38 #include "qemu/error-report.h"
58 * The BIOS image used by this machine is called Hart Software Services (HSS).
59 * See https://github.com/polarfire-soc/hart-software-services
76 * https://www.microsemi.com/document-portal/doc_download/
77 * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
81 * https://www.microsemi.com/document-portal/doc_download/
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| H A D | virt.c | 2 * QEMU RISC-V VirtIO Board
6 * RISC-V machine with 16550a UART and VirtIO MMIO
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial-mm.h"
32 #include "hw/core/sysbus-fdt.h"
45 #include "hw/platform-bus.h"
54 #include "hw/pci-host/gpex.h"
56 #include "hw/acpi/aml-build.h"
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| H A D | spike.c | 2 * QEMU RISC-V Spike Board
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This provides a RISC-V Board with the following devices:
26 #include "qemu/error-report.h"
68 fdt = ms->fdt = create_device_tree(&fdt_size); in create_fdt()
74 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); in create_fdt()
75 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); in create_fdt()
76 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()
77 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); in create_fdt()
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| H A D | opentitan.c | 2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
6 * Provides a board compatible with the OpenTitan FPGA platform:
25 #include "qemu/error-report.h"
85 if (machine->ram_size != mc->default_ram_size) { in opentitan_machine_init()
86 char *sz = size_to_str(mc->default_ram_size); in opentitan_machine_init()
93 object_initialize_child(OBJECT(machine), "soc", &s->soc, in opentitan_machine_init()
95 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); in opentitan_machine_init()
98 memmap[IBEX_DEV_RAM].base, machine->ram); in opentitan_machine_init()
100 if (machine->firmware) { in opentitan_machine_init()
102 riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL); in opentitan_machine_init()
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| /openbmc/linux/Documentation/devicetree/bindings/iio/temperature/ |
| H A D | adi,ltc2983.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices LTC2983, LTC2986, LTM2985 Multi-sensor Temperature system
10 - Nuno Sá <nuno.sa@analog.com>
13 Analog Devices LTC2983, LTC2984, LTC2986, LTM2985 Multi-Sensor Digital
16 https://www.analog.com/media/en/technical-documentation/data-sheets/2983fc.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/2984fb.pdf
18 https://www.analog.com/media/en/technical-documentation/data-sheets/29861fa.pdf
19 https://www.analog.com/media/en/technical-documentation/data-sheets/ltm2985.pdf
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| /openbmc/linux/drivers/cpuidle/ |
| H A D | cpuidle-riscv-sbi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V SBI CPU idle driver.
9 #define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt
52 data->available = true; in sbi_set_domain_state()
53 data->state = state; in sbi_set_domain_state()
60 return data->state; in sbi_get_domain_state()
67 data->available = false; in sbi_clear_domain_state()
74 return data->available; in sbi_is_domain_state_available()
115 u32 *states = data->states; in __sbi_enter_domain_idle_state()
116 struct device *pd_dev = data->dev; in __sbi_enter_domain_idle_state()
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| /openbmc/linux/arch/riscv/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
169 # https://github.com/llvm/llvm-project/commit/6ab8927931851bb42b2c93a00801dc499d7d9b1e
176 depends on $(cc-option,-fpatchable-function-entry=8)
186 # VA_BITS - PAGE_SHIFT - 3
199 # set if we are running in S-mode and can use SBI calls
206 bool "MMU-based Paged Memory Management Support"
209 Select if you want MMU-based virtualised addressing space
286 This enables function pointer support for non-standard noncoherent
290 def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero)
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| /openbmc/linux/drivers/clk/microchip/ |
| H A D | clk-mpfs.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/microchip,mpfs-clock.h>
99 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
100 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
101 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; in mpfs_clk_msspll_recalc_rate()
117 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_round_rate()
118 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_round_rate()
130 msspll_hw->flags); in mpfs_clk_msspll_round_rate()
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| /openbmc/linux/drivers/iio/addac/ |
| H A D | ad74413r.c | 1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/iio/addac/adi,ad74413r.h>
64 * Synchronize consecutive operations when doing a one-shot
176 ad74413r_format_reg_write(reg, val, st->reg_tx_buf); in ad74413r_reg_write()
178 return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE); in ad74413r_reg_write()
186 dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n", in ad74413r_crc_check()
188 return -EINVAL; in ad74413r_crc_check()
199 .tx_buf = st->reg_tx_buf, in ad74413r_reg_read()
204 .rx_buf = st->reg_rx_buf, in ad74413r_reg_read()
211 st->reg_tx_buf); in ad74413r_reg_read()
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| /openbmc/linux/drivers/acpi/ |
| H A D | property.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Darren Hart <dvhart@linux.intel.com>
33 /* ACPI _DSD device properties GUID: daffd814-6eba-4d8c-8a91-bc9bbf4aa301 */
36 /* Hotplug in D3 GUID: 6211e2c0-58a3-4af3-90e1-927a4e0c55a4 */
39 /* External facing port GUID: efcc06cc-73ac-4bc3-bff0-76143807c389 */
42 /* Thunderbolt GUID for IMR_VALID: c44d002f-69f9-4e7d-a904-a7baabdf43f7 */
45 /* Thunderbolt GUID for WAKE_SUPPORTED: 6c501103-c189-4296-ba72-9bf5a26ebe5d */
48 /* Storage device needs D3 GUID: 5025030f-842f-4ab4-a561-99a5189762d0 */
53 /* ACPI _DSD data subnodes GUID: dbb8e3e6-5886-4ba6-8795-1319f52a966b */
83 dn->name = link->package.elements[0].string.pointer; in acpi_nondev_subnode_extract()
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