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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmvebu-gated-clock.txt7 corresponding clock gating control bit in HW to ease manual clock
177 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 "marvell,dove-gating-clock" - for Dove SoC clock gating
184 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
[all …]
/openbmc/u-boot/board/gateworks/gw_ventana/
H A Dgw_ventana_spl.c211 /* Read DQS Gating calibration */
227 /* Read DQS Gating calibration */
247 /* Read DQS Gating calibration */
264 /* Read DQS Gating calibration */
277 /* Read DQS Gating calibration */
290 /* Read DQS Gating calibration */
303 /* Read DQS Gating calibration */
318 /* Read DQS Gating calibration */
337 /* Read DQS Gating calibration */
354 /* Read DQS Gating calibration */
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dclk-branch.h13 * struct clk_branch - gating clock with status bit and dynamic hardware gating
15 * @hwcg_reg: dynamic hardware clock gating register
16 * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h121 * Gating control and status is managed by a 32-bit gate register.
123 * There are several types of gating available:
126 * - hardware-only gating (auto-gating)
131 * - software-only gating
132 * Auto-gating is not available for this type of clock.
136 * To ensure a change to the gating status is complete, the
139 * - selectable hardware or software gating
140 * Gating for this type of clock can be configured to be either
148 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h121 * Gating control and status is managed by a 32-bit gate register.
123 * There are several types of gating available:
126 * - hardware-only gating (auto-gating)
131 * - software-only gating
132 * Auto-gating is not available for this type of clock.
136 * To ensure a change to the gating status is complete, the
139 * - selectable hardware or software gating
140 * Gating for this type of clock can be configured to be either
148 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
/openbmc/linux/sound/soc/intel/catpt/
H A Ddsp.c169 /* wait for SRAM power gating to propagate */ in catpt_dsp_set_srampge()
207 /* disable core clock gating */ in catpt_dsp_update_srampge()
212 /* enable core clock gating */ in catpt_dsp_update_srampge()
361 /* disable core clock gating */ in catpt_dsp_power_down()
374 /* switch clock gating */ in catpt_dsp_power_down()
382 /* SRAM power gating all */ in catpt_dsp_power_down()
394 /* enable core clock gating */ in catpt_dsp_power_down()
406 /* disable core clock gating */ in catpt_dsp_power_up()
409 /* switch clock gating */ in catpt_dsp_power_up()
416 /* SRAM power gating none */ in catpt_dsp_power_up()
[all …]
/openbmc/linux/drivers/soc/tegra/
H A Dflowctrl.c84 /* pwr gating on wfe */ in flowctrl_cpu_suspend_enter()
99 * power-gating (like memory running off PLLP), in flowctrl_cpu_suspend_enter()
103 * while wfe for the power-gating, just like it in flowctrl_cpu_suspend_enter()
108 /* pwr gating on wfi */ in flowctrl_cpu_suspend_enter()
115 reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ in flowctrl_cpu_suspend_enter()
/openbmc/linux/drivers/clk/bcm/
H A Dclk-kona.h98 * Gating control and status is managed by a 32-bit gate register.
100 * There are several types of gating available:
103 * - hardware-only gating (auto-gating)
108 * - software-only gating
109 * Auto-gating is not available for this type of clock.
113 * To ensure a change to the gating status is complete, the
116 * - selectable hardware or software gating
117 * Gating for this type of clock can be configured to be either
125 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dlpddr2.h57 #define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
58 #define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */
62 #define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
63 #define MMDC_MPDGCTRL1_MODULE1_VALUE 0x00000000 /* Read DQS gating control 1 */
/openbmc/linux/drivers/pmdomain/st/
H A Dste-ux500-pm-domain.c23 * Handle the gating of the PM domain regulator here. in pd_power_off()
27 * callbacks, to be able to enable PM domain gating/ungating. in pd_power_off()
39 * callbacks, to be able to enable PM domain gating/ungating. in pd_power_on()
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_device.c89 u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL); in psb_init_pm() local
90 gating &= ~3; /* Disable 2D clock gating */ in psb_init_pm()
91 gating |= 1; in psb_init_pm()
92 PSB_WSGX32(gating, PSB_CR_CLKGATECTL); in psb_init_pm()
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.c293 /* TGL only supports slice-level power gating */ in gen12_sseu_info_init()
325 /* ICL has no power gating restrictions. */ in gen11_sseu_info_init()
374 * CHV supports subslice power gating on devices with more than in cherryview_sseu_info_init()
375 * one subslice, and supports EU power gating on devices with in cherryview_sseu_info_init()
459 * SKL+ supports slice power gating on devices with more than in gen9_sseu_info_init()
460 * one slice, and supports EU power gating on devices with in gen9_sseu_info_init()
462 * power gating on devices with more than one subslice, and in gen9_sseu_info_init()
463 * supports EU power gating on devices with more than one EU in gen9_sseu_info_init()
566 * BDW supports slice power gating on devices with more than in bdw_sseu_info_init()
722 * Starting in Gen9, render power gating can leave in intel_sseu_make_rpcs()
[all …]
/openbmc/linux/drivers/platform/x86/intel/pmc/
H A DKconfig20 - PCH IP Power Gating status
22 - MPHY/PLL gating status (Sunrisepoint PCH only)
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0.c535 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating
540 * Disable static power gating for VCN block
600 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating
605 * Enable static power gating for VCN block
655 * vcn_v4_0_disable_clock_gating - disable VCN clock gating
660 * Disable clock gating for VCN block
766 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
773 * Disable clock gating for VCN block with dpg mode
783 /* enable sw clock gating control */ in vcn_v4_0_disable_clock_gating_dpg_mode()
809 /* turn off clock gating */ in vcn_v4_0_disable_clock_gating_dpg_mode()
[all …]
H A Dvcn_v4_0_3.c525 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating
530 * Disable clock gating for VCN block
618 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
625 * Disable clock gating for VCN block with dpg mode
635 /* enable sw clock gating control */ in vcn_v4_0_3_disable_clock_gating_dpg_mode()
655 /* turn off clock gating */ in vcn_v4_0_3_disable_clock_gating_dpg_mode()
659 /* turn on SUVD clock gating */ in vcn_v4_0_3_disable_clock_gating_dpg_mode()
669 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating
674 * Enable clock gating for VCN block
740 /* enable dynamic power gating mode */ in vcn_v4_0_3_start_dpg_mode()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dhardwaremanager.h94 …PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or…
95 …PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Sh…
97 PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */
147 …PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from…
148 …PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, suppor…
149 …PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for …
150 …PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for…
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.h36 * 0=Default, use auto-clock gating to save power;
37 * 1=use free-run clock, disable auto-clock gating, for debug mode.
39 * have auto-clock gating. 1=Enable pixclk. Default 0.
41 * have auto-clock gating. 1=Enable sysclk. Default 0.
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c356 * bits [31:26] - DQS gating system latency for byte lane 3
357 * bits [25:24] - DQS gating phase select for byte lane 3
358 * bits [23:18] - DQS gating system latency for byte lane 2
359 * bits [17:16] - DQS gating phase select for byte lane 2
360 * bits [15:10] - DQS gating system latency for byte lane 1
361 * bits [ 9:8 ] - DQS gating phase select for byte lane 1
362 * bits [ 7:2 ] - DQS gating system latency for byte lane 0
363 * bits [ 1:0 ] - DQS gating phase select for byte lane 0
369 /* rank0 gating system latency (3 bits per lane: cycles) */ in mctl_set_dqs_gating_delay()
371 /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */ in mctl_set_dqs_gating_delay()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun9i.h83 u32 ahb_gate0; /* 0x580 AHB0 Gating Register */
84 u32 ahb_gate1; /* 0x584 AHB1 Gating Register */
85 u32 ahb_gate2; /* 0x588 AHB2 Gating Register */
87 u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */
88 u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */
H A Dclock_sun8i_a83t.h38 u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
39 u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
40 u32 apb1_gate; /* 0x68 apb1 module clock gating 3 */
41 u32 apb2_gate; /* 0x6c apb2 module clock gating 4 */
67 u32 dram_clk_gate; /* 0x100 DRAM module gating */
/openbmc/linux/sound/pci/hda/
H A Dhda_jack.c207 /* A gating jack indicates the jack is invalid if gating is unplugged */ in jack_detect_update()
376 * snd_hda_jack_set_gating_jack - Set gating jack.
379 * @gating_nid: gating pin NID
381 * Indicates the gated jack is only valid when the gating jack is plugged.
387 struct hda_jack_tbl *gating = in snd_hda_jack_set_gating_jack() local
392 if (!gated || !gating) in snd_hda_jack_set_gating_jack()
396 gating->gated_jack = gated_nid; in snd_hda_jack_set_gating_jack()
481 * to make sure that all gating jacks properly have been set in snd_hda_jack_report_sync()
/openbmc/linux/drivers/media/dvb-frontends/
H A Ddib3000mc.h48 int gating);
69 int gating) in dib3000mc_get_tuner_i2c_master() argument
/openbmc/linux/sound/soc/sof/intel/
H A Dhda-ipc.h43 /* Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */
45 /* Prevent power gating (0 - deep power state transitions allowed) */
H A Dhda-ctrl.c156 * enable/disable audio dsp clock gating and power gating bits.
165 /* enable/disable audio dsp clock gating */ in hda_dsp_ctrl_clock_power_gating()
175 /* enable/disable audio dsp power gating */ in hda_dsp_ctrl_clock_power_gating()
/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_clock_gating.c134 * gating for the panel power sequencer or it will fail to in ibx_init_clock_gating()
214 * gating for the panel power sequencer or it will fail to in cpt_init_clock_gating()
266 * gating disable must be set. Failure to set it results in in gen6_init_clock_gating()
344 * Wait at least 100 clocks before re-enabling clock gating. in gen8_set_l3sqc_credits()
547 * clock gating. in bdw_init_clock_gating()
646 * Disabling L3 clock gating- MMIO 940c[25] = 1 in vlv_init_clock_gating()
652 * Disable clock gating on th GCFG unit to prevent a delay in vlv_init_clock_gating()
792 "No clock gating settings or workarounds applied.\n"); in nop_init_clock_gating()
828 * intel_clock_gating_hooks_init - setup the clock gating hooks

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