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/openbmc/qemu/hw/intc/
H A Dtrace-events113 gicv3_icc_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR read cpu 0x%x value 0x%" PRIx64
114 gicv3_icc_pmr_write(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR write cpu 0x%x value 0x%" PRIx64
115 gicv3_icc_bpr_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_BPR%d read cpu 0x%x value 0x%" P…
116 gicv3_icc_bpr_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_BPR%d write cpu 0x%x value 0x%"…
117 gicv3_icc_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICC_AP%dR%d read cpu 0x%x …
118 gicv3_icc_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICC_AP%dR%d write cpu 0x%…
119 gicv3_icc_igrpen_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN%d read cpu 0x%x value …
120 gicv3_icc_igrpen_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN%d write cpu 0x%x valu…
121 gicv3_icc_igrpen1_el3_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN1_EL3 read cpu 0x%x value 0…
122 gicv3_icc_igrpen1_el3_write(uint32_t cpu, uint64_t val) "GICv3 ICC_IGRPEN1_EL3 write cpu 0x%x value…
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H A Darm_gicv3_its.c2 * ITS emulation for a GICv3-based system
145 AddressSpace *as = &s->gicv3->dma_as; in table_entry_addr()
182 AddressSpace *as = &s->gicv3->dma_as; in get_cte()
216 AddressSpace *as = &s->gicv3->dma_as; in update_ite()
252 AddressSpace *as = &s->gicv3->dma_as; in get_ite()
291 AddressSpace *as = &s->gicv3->dma_as; in get_dte()
326 AddressSpace *as = &s->gicv3->dma_as; in get_vte()
427 if (cte->rdbase >= s->gicv3->num_cpu) { in lookup_cte()
459 if (vte->rdbase >= s->gicv3->num_cpu) { in lookup_vte()
475 gicv3_redist_process_lpi(&s->gicv3->cpu[cte.rdbase], ite->intid, irqlevel); in process_its_cmd_phys()
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H A Darm_gicv3_its_kvm.c2 * KVM-based ITS implementation for a GICv3-based system
110 gicv3_add_its(s->gicv3, dev); in kvm_arm_its_realize()
238 DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "kvm-arm-gicv3",
H A Darm_gicv3_common.c2 * ARM GICv3 support - common bits of emulated and KVM kernel model
8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
44 * to the KVM GICv3: they got the offset in the bitmap arrays wrong, in gicv3_gicd_no_migration_shift_bug_post_load()
433 "gicv3-its-sysmem"); in arm_gicv3_common_realize()
664 return "kvm-arm-gicv3"; in type_init()
667 error_report("Userspace GICv3 is not supported with KVM"); in type_init()
670 return "arm-gicv3"; in type_init()
H A Dgicv3_internal.h2 * ARM GICv3 support - internal interfaces
8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
62 #define GICD_CTLR_EN_GRP1NS (1U << 1) /* GICv3 5.3.20 */
454 * as per Table 5.3 in GICv3 spec
525 /* Functions internal to the emulated GICv3 */
751 * for the emulated GICv3, as reported in GICD_IIDR and GICR_IIDR. in gicv3_iidr()
759 /* CoreSight PIDR0 values for ARM GICv3 implementations */
769 * These values indicate an ARM implementation of a GICv3 or v4. in gicv3_idreg()
H A Darm_gicv3_its_common.c2 * ITS base class for a GICv3-based system
169 return "arm-gicv3-its"; in type_init()
/openbmc/qemu/include/hw/intc/
H A Darm_gicv3_its_common.h2 * ITS support for ARM GICv3
28 #define TYPE_ARM_GICV3_ITS "arm-gicv3-its"
64 GICv3State *gicv3; member
110 #define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
H A Darm_gicv3_common.h8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
42 * The redistributor in GICv3 has two 64KB frames per CPU; in
303 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
323 * Return name of GICv3 class to use depending on whether KVM acceleration is
H A Darm_gicv3.h18 #define TYPE_ARM_GICV3 "arm-gicv3"
/openbmc/linux/include/kvm/
H A Darm_vgic.h40 VGIC_V3, /* New fancy GICv3 */
77 /* Pseudo GICv3 from outer space */
146 u32 mpidr; /* GICv3 target VCPU */
229 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
235 #define KVM_VGIC_IMP_REV_3 3 /* GICv3 GICR_CTLR.{IW,CES,RWP} */
251 /* or a number of GICv3 redistributor regions */
272 * GICv3 spec: IHI 0069E 6.1.1 "LPI Configuration tables"
345 * Members below are used with GICv3 emulation only and represent
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dfoundation-v8-gicv3-psci.dts4 * ARMv8 Foundation model DTS (GICv3+PSCI configuration)
8 #include "foundation-v8-gicv3.dtsi"
H A Dfoundation-v8-gicv3.dts5 * ARMv8 Foundation model DTS (GICv3 configuration)
9 #include "foundation-v8-gicv3.dtsi"
H A DMakefile4 foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb
H A Dfoundation-v8-gicv3.dtsi4 * ARMv8 Foundation model DTS (GICv3 configuration)
/openbmc/linux/arch/arm64/kvm/vgic/
H A Dvgic-v3.c207 * When emulating GICv3 on GICv3 with SRE=1 on the in vgic_v3_set_vmcr()
239 * When emulating GICv3 on GICv3 with SRE=1 on the in vgic_v3_get_vmcr()
272 * If we are emulating a GICv3, we do it in an non-GICv2-compatible in vgic_v3_enable()
661 kvm_info("GICv3: no GICV resource entry\n"); in vgic_v3_probe()
679 kvm_err("Cannot register GICv3 KVM device.\n"); in vgic_v3_probe()
693 kvm_info("GICv3 with broken locally generated SEI\n"); in vgic_v3_probe()
705 kvm_info("GICv3 sysreg trapping enabled ([%s%s%s%s], reduced performance)\n", in vgic_v3_probe()
725 * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen in vgic_v3_load()
/openbmc/qemu/docs/system/arm/
H A Dvirt.rst37 with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note
42 - many CPUs (up to 512 if using a GICv3 and highmem)
129 Set ``on``/``off`` to enable/disable the high memory region for GICv3 or
131 limit the maximum number of CPUs when GICv3 or GICv4 is used.
148 GICv3. This allows up to 512 CPUs.
/openbmc/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst14 possible to create both a GICv3 and GICv2 on the same VM.
16 Creating a guest GICv3 device requires a host GICv3 as well.
24 Base address in the guest physical address space of the GICv3 distributor
29 Base address in the guest physical address space of the GICv3
96 in the GICv3/4 specs. Getting or setting such a register has the same
147 rules are documented in the GICv3 specification descriptions of the ICPENDR
H A Darm-vgic-its.rst11 optional. Creating a virtual ITS controller also requires a host GICv3 (see
26 Base address in the guest physical address space of the GICv3 ITS
66 The GICV3 must be restored before the ITS and all ITS registers but
73 The expected ordering when restoring the GICv3/ITS is described in section
147 Revision 0 of the ABI only supports the features of a virtual GICv3, and does
H A Darm-vgic.rst16 GICv3 implementations with hardware compatibility support allow creating a
17 guest GICv2 through this interface. For information on creating a guest GICv3
19 create both a GICv3 and GICv2 device on the same VM.
/openbmc/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dbooting.txt195 對於擁有 GICv3 中斷控制器並以 v3 模式運行的系統：
202 - 設備樹（DT）或 ACPI 表必須描述一個 GICv3 中斷控制器。
204 對於擁有 GICv3 中斷控制器並以兼容（v2）模式運行的系統：
/openbmc/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dbooting.txt191 对于拥有 GICv3 中断控制器并以 v3 模式运行的系统：
198 - 设备树（DT）或 ACPI 表必须描述一个 GICv3 中断控制器。
200 对于拥有 GICv3 中断控制器并以兼容（v2）模式运行的系统：
/openbmc/u-boot/arch/arm/lib/
H A Dgic_64.S70 * For Gicv3:
165 * For Gicv3:
186 * For Gicv3:
/openbmc/linux/drivers/irqchip/
H A Dirq-gic-v3.c7 #define pr_fmt(fmt) "GICv3: " fmt
96 * see GICv3/GICv4 Architecture Specification (IHI0069D):
934 /* Extended SPI range, not handled by the GICv2/GICv3 common code */ in gic_dist_init()
1117 pr_info("GICv3 features: %d PPIs%s%s\n", in gic_update_rdist_properties()
1395 "irqchip/arm/gicv3:starting", in gic_smp_init()
1488 .name = "GICv3",
1506 .name = "GICv3",
1877 .desc = "GICv3: Qualcomm MSM8996 broken firmware",
1882 .desc = "GICv3: ASR erratum 8601001",
1887 .desc = "GICv3: Mediatek Chromebook GICR save problem",
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/openbmc/u-boot/arch/arm/mach-versal/
H A DKconfig24 config GICV3 config
/openbmc/linux/include/linux/irqchip/
H A Darm-vgic-info.h16 /* Full GICv3, optionally with v2 compat */

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