Searched full:gics (Results 1 – 9 of 9) sorted by relevance
18 Secondary GICs are cascaded into the upward interrupt controller and do not113 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
29 /* The GICs on the RealView boards have a fixed nonconfigurable in realview_gic_realize()
305 /* For uniprocessor GICs all interrupts always target the sole CPU */ in arm_gic_common_reset_hold()
1081 /* For uniprocessor GICs these RAZ/WI */ in gic_dist_readb()1217 * GIC, or for GICs without groups. in gic_dist_writeb()1404 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the in gic_dist_writeb()
144 * chips and call this to register their GICs.
48 * "performance interrupt". Luckily, on compliant GICs the polarity is in arm_pmu_acpi_register_irq()
700 MADT for GICs are expected to be in synchronization. The _UID of the Device769 - Section 9.17: I/O APIC devices; all GICs must be enumerable via MADT
580 * If we get one of these oddball non-GICs, taint the kernel, in kvm_vgic_hyp_init()
499 * because any nested/secondary GICs do not directly interface in gic_cpu_init()