Searched full:fmreg (Results 1 – 3 of 3) sorted by relevance
23 0x0100 FMREG40 0x0100 FMREG49 0x1100 FMREG60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back62 added on V2; the FMREG bank for slew rate calibration is not used anymore
21 0x0100 FMREG24 0x1100 FMREG
295 void __iomem *fmreg; member698 void __iomem *fmreg = u2_banks->fmreg; in hs_slew_rate_calibrate() local717 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in hs_slew_rate_calibrate()720 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()726 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()729 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in hs_slew_rate_calibrate()732 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, in hs_slew_rate_calibrate()735 fm_out = readl(fmreg + U3P_U2FREQ_VALUE); in hs_slew_rate_calibrate()738 mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); in hs_slew_rate_calibrate()741 mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); in hs_slew_rate_calibrate()[all …]