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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc53 architecture combining eight ARM A53 processor cores
84 The LS2080A integrated multicore processor combines eight ARM Cortex-A57
91 - Eight 64-bit ARM Cortex-A57 CPUs
108 - Up to eight 10 Gbps Ethernet MACs
109 - Up to eight 1 / 2.5 Gbps Ethernet MACs
211 The LS2088A integrated multicore processor combines eight ARM Cortex-A72
218 - Eight 64-bit ARM Cortex-A72 CPUs
235 - Up to eight 10 Gbps Ethernet MACs
236 - Up to eight 1 / 2.5 Gbps Ethernet MACs
311 Eight I2C Controllers.
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/openbmc/linux/Documentation/admin-guide/media/
H A Dcec.rst41 - Pulse-Eight: the pulse8-cec driver implements the following module option:
46 module option of the Pulse-Eight driver. The hardware supports it, but I
82 Note that the libcec library (https://github.com/Pulse-Eight/libcec) supports
156 utility to create the ``/dev/cecX`` devices. Support for the Pulse-Eight
168 For Pulse-Eight make /lib/systemd/system/pulse8-cec-inputattach@.service::
195 …ExecStart=/bin/bash -c 'for d in /dev/serial/by-id/usb-Pulse-Eight*; do /usr/bin/inputattach --dae…
243 1) Get a Pulse-Eight USB CEC dongle, connect an HDMI cable from your
244 device to the Pulse-Eight, but do not connect the Pulse-Eight to
247 Now configure the Pulse-Eight dongle::
264 The Pulse-Eight should see the <Image View On> message. If not,
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/openbmc/linux/arch/arm/include/asm/
H A Ducontext.h26 /* Last for extensibility. Eight byte aligned because some
27 coprocessors require eight byte alignment. */
36 * these should be a multiple of eight bytes and aligned to eight
/openbmc/linux/Documentation/arch/mips/
H A Dingenic-tcu.rst8 hardware block. It features up to eight channels, that can be used as
12 have eight channels.
35 - On the oldest SoCs (up to JZ4740), all of the eight channels operate in
49 channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
/openbmc/linux/drivers/media/cec/usb/pulse8/
H A DKconfig3 tristate "Pulse Eight HDMI CEC"
10 This is a cec driver for the Pulse Eight HDMI CEC device.
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/p8platform/
H A Dp8platform_git.bb2 HOMEPAGE = "http://libcec.pulse-eight.com/"
9 SRC_URI = "git://github.com/Pulse-Eight/platform.git;branch=master;protocol=https"
/openbmc/linux/Documentation/hwmon/
H A Daquacomputer_d5next.rst28 The Aquaero devices expose eight physical, eight virtual and four calculated
34 and current, as well as coolant temperature and eight virtual temp sensors. Also
47 eight PWM controllable fans, along with their speed (in RPM), power, voltage and
H A Dmax16065.rst57 simultaneously, and the MAX16066 manages up to eight supply voltages.
69 monitors up to eight supply voltages.
/openbmc/linux/include/linux/platform_data/
H A Dmax3421-hcd.h14 * MAX3421E GPIO pins. The chip has eight GP inputs and eight GP outputs.
/openbmc/linux/Documentation/ABI/stable/
H A Dsysfs-driver-ib_srp10 * id_ext, a 16-digit hexadecimal number specifying the eight
14 * ioc_guid, a 16-digit hexadecimal number specifying the eight
125 Description: Eight-byte identifier extension portion of the 16-byte target
132 Description: Eight-byte I/O controller GUID portion of the 16-byte target
/openbmc/u-boot/include/
H A Dmpc8xx_irq.h4 /* The MPC8xx cores have 16 possible interrupts. There are eight
7 * There are eight external interrupts (IRQs) that can be configured
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/libcec/
H A Dlibcec_6.0.2.bb2 HOMEPAGE = "http://libcec.pulse-eight.com/"
13 SRC_URI = "git://github.com/Pulse-Eight/libcec.git;branch=release;protocol=https \
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsamsung,exynos4210-combiner.yaml18 The interrupt combiner controller consists of multiple combiners. Up to eight
20 combined interrupt for its eight interrupt sources. The combined interrupt is
/openbmc/linux/arch/x86/crypto/
H A DKconfig113 Processes eight blocks in parallel.
143 Processes eight blocks in parallel.
176 Processes eight blocks in parallel.
287 Processes eight blocks in parallel.
/openbmc/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A Dpipeline.json21 … in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable count…
29 …halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreadin…
36 …n the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable count…
/openbmc/linux/Documentation/admin-guide/perf/
H A Dalibaba_pmu.rst12 Yitian 710 employs eight DDR5/4 channels, four on each die. Each DDR5 channel
31 to count the total access number of either the eight bank groups in a
/openbmc/linux/Documentation/networking/
H A Darcnet-hardware.rst125 to other segments of the net. They usually have eight connectors. Active
640 The eight switches in group S2 are used to set the node ID.
649 of eight possible I/O Base addresses using the following table::
669 16K block can be located in any of eight positions.
848 The eight switches in group SW3 are used to set the node ID. Each node
934 from 0 to 15 would be possible, but only the following eight values will
1227 There is another array of eight DIP switches at the top of the
1377 The eight switches in SW2 are used to set the node ID. Each node attached
1420 of eight possible I/O Base addresses using the following table::
1440 located in any of eight positions. The address of the Boot Prom is
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/openbmc/u-boot/drivers/nvme/
H A Dnvme_show.c84 printf("\tAs last eight bytes: %s\n", in print_data_protect_cap()
86 printf("\tAs first eight bytes: %s\n", in print_data_protect_cap()
/openbmc/linux/Documentation/admin-guide/
H A Dunicode.rst16 both the eight-bit character sets and UTF-8 mode are changed to use
19 This changes the semantics of the eight-bit character tables subtly.
164 U+F8F8 KLINGON DIGIT EIGHT
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Ddigicolor-wdt.txt4 "Agent Communication" block. This block includes the eight programmable system
/openbmc/linux/arch/s390/mm/
H A Dmaccess.c58 * Therefore we have a read-modify-write sequence: the function reads eight
59 * bytes from destination at an eight byte boundary, modifies the bytes
/openbmc/linux/include/crypto/
H A Dtwofish.h14 * S-boxes composed with the MDS matrix; w contains the eight "whitening"
/openbmc/pldm/libpldmresponder/test/pdr_jsons/state_sensor/malformed/
H A Dsensor_pdr.json8 // supported event states, up to eight.
/openbmc/linux/drivers/rtc/
H A Drtc-tegra.c21 /* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
59 * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
74 * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/hplip/hplip/
H A D0001-Drop-using-register-storage-classifier.patch93 /* We allocate one big table and divide it up into eight parts, instead of
94 * doing eight alloc_small requests. This lets us use a single table base
97 * machines (more than can hold all eight addresses, anyway).

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