14a5b6a35Swdenk #ifndef _MPC8XX_IRQ_H 24a5b6a35Swdenk #define _MPC8XX_IRQ_H 34a5b6a35Swdenk 44a5b6a35Swdenk /* The MPC8xx cores have 16 possible interrupts. There are eight 54a5b6a35Swdenk * possible level sensitive interrupts assigned and generated internally 64a5b6a35Swdenk * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. 74a5b6a35Swdenk * There are eight external interrupts (IRQs) that can be configured 84a5b6a35Swdenk * as either level or edge sensitive. 94a5b6a35Swdenk * 104a5b6a35Swdenk * On some implementations, there is also the possibility of an 8259 114a5b6a35Swdenk * through the PCI and PCI-ISA bridges. 124a5b6a35Swdenk * 134a5b6a35Swdenk * We don't support the 8259 (yet). 144a5b6a35Swdenk */ 154a5b6a35Swdenk #define NR_SIU_INTS 16 164a5b6a35Swdenk #define NR_8259_INTS 0 174a5b6a35Swdenk 184a5b6a35Swdenk #define NR_IRQS (NR_SIU_INTS + NR_8259_INTS) 194a5b6a35Swdenk 204a5b6a35Swdenk /* These values must be zero-based and map 1:1 with the SIU configuration. 214a5b6a35Swdenk * They are used throughout the 8xx I/O subsystem to generate 224a5b6a35Swdenk * interrupt masks, flags, and other control patterns. This is why the 234a5b6a35Swdenk * current kernel assumption of the 8259 as the base controller is such 244a5b6a35Swdenk * a pain in the butt. 254a5b6a35Swdenk */ 264a5b6a35Swdenk #define SIU_IRQ0 (0) /* Highest priority */ 274a5b6a35Swdenk #define SIU_LEVEL0 (1) 284a5b6a35Swdenk #define SIU_IRQ1 (2) 294a5b6a35Swdenk #define SIU_LEVEL1 (3) 304a5b6a35Swdenk #define SIU_IRQ2 (4) 314a5b6a35Swdenk #define SIU_LEVEL2 (5) 324a5b6a35Swdenk #define SIU_IRQ3 (6) 334a5b6a35Swdenk #define SIU_LEVEL3 (7) 344a5b6a35Swdenk #define SIU_IRQ4 (8) 354a5b6a35Swdenk #define SIU_LEVEL4 (9) 364a5b6a35Swdenk #define SIU_IRQ5 (10) 374a5b6a35Swdenk #define SIU_LEVEL5 (11) 384a5b6a35Swdenk #define SIU_IRQ6 (12) 394a5b6a35Swdenk #define SIU_LEVEL6 (13) 404a5b6a35Swdenk #define SIU_IRQ7 (14) 414a5b6a35Swdenk #define SIU_LEVEL7 (15) 424a5b6a35Swdenk 434a5b6a35Swdenk /* The internal interrupts we can configure as we see fit. 444a5b6a35Swdenk * My personal preference is CPM at level 2, which puts it above the 454a5b6a35Swdenk * MBX PCI/ISA/IDE interrupts. 464a5b6a35Swdenk */ 474a5b6a35Swdenk 48*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_CPM_INTERRUPT 49*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CPM_INTERRUPT CONFIG_SYS_CPM_INTERRUPT 504a5b6a35Swdenk #else 514a5b6a35Swdenk # define CPM_INTERRUPT SIU_LEVEL2 524a5b6a35Swdenk #endif 534a5b6a35Swdenk 544a5b6a35Swdenk /* Some internal interrupt registers use an 8-bit mask for the interrupt 554a5b6a35Swdenk * level instead of a number. 564a5b6a35Swdenk */ 574a5b6a35Swdenk #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) 584a5b6a35Swdenk 594a5b6a35Swdenk #endif /* _MPC8XX_IRQ_H */ 60