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/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Dx1000.dtsi43 exclk: ext { label
63 clocks = <&exclk>, <&rtclk>;
230 clocks = <&exclk>, <&cgu X1000_CLK_UART0>;
243 clocks = <&exclk>, <&cgu X1000_CLK_UART1>;
256 clocks = <&exclk>, <&cgu X1000_CLK_UART2>;
H A Dx1830.dtsi43 exclk: ext { label
63 clocks = <&exclk>, <&rtclk>;
225 clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
238 clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
H A Dcu1830-neo.dts42 &exclk {
H A Dcu1000-neo.dts42 &exclk {
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,rzg2l-cpg.yaml40 Clock source to CPG can be either from external clock input (EXCLK) or
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c318 #define CPM_OPCR_ERCS BIT(2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
319 #define CPM_OPCR_USBM BIT(0) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g011.dtsi16 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
H A Dr9a07g043.dtsi36 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
H A Dr9a07g054.dtsi37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
H A Dr9a07g044.dtsi37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
/openbmc/linux/drivers/clk/ingenic/
H A Dx1000-cgu.c381 * Therefore, the divider is disabled when EXCLK is selected.
/openbmc/qemu/hw/misc/
H A Domap_clk.c477 .name = "cam.exclk",