| /openbmc/linux/drivers/spi/ |
| H A D | spi-fsl-espi.c | 3 * Freescale eSPI controller driver.
22 /* eSPI Controller registers */
23 #define ESPI_SPMODE 0x00 /* eSPI mode register */
24 #define ESPI_SPIE 0x04 /* eSPI event register */
25 #define ESPI_SPIM 0x08 /* eSPI mask register */
26 #define ESPI_SPCOM 0x0c /* eSPI command register */
27 #define ESPI_SPITF 0x10 /* eSPI transmit FIFO access register*/
28 #define ESPI_SPIRF 0x14 /* eSPI receive FIFO access register*/
29 #define ESPI_SPMODE0 0x20 /* eSPI cs0 mode register */
33 /* eSPI Controller mode register definitions */
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| H A D | spi-ep93xx.c | 115 struct ep93xx_spi *espi = spi_controller_get_devdata(host); in ep93xx_spi_calc_divisors() local
116 unsigned long spi_clk_rate = clk_get_rate(espi->clk); in ep93xx_spi_calc_divisors()
150 struct ep93xx_spi *espi = spi_controller_get_devdata(host); in ep93xx_spi_chip_setup() local
173 writel(div_cpsr, espi->mmio + SSPCPSR); in ep93xx_spi_chip_setup()
174 writel(cr0, espi->mmio + SSPCR0); in ep93xx_spi_chip_setup()
181 struct ep93xx_spi *espi = spi_controller_get_devdata(host); in ep93xx_do_write() local
187 val = ((u16 *)xfer->tx_buf)[espi->tx]; in ep93xx_do_write()
188 espi->tx += 2; in ep93xx_do_write()
191 val = ((u8 *)xfer->tx_buf)[espi->tx]; in ep93xx_do_write()
192 espi->tx += 1; in ep93xx_do_write()
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| /openbmc/linux/drivers/net/ethernet/chelsio/cxgb/ |
| H A D | espi.c | 4 * File: espi.c *
32 #include "espi.h"
79 pr_err("%s: ESPI clock not ready\n", adapter->name); in tricn_init()
108 void t1_espi_intr_enable(struct peespi *espi) in t1_espi_intr_enable() argument
110 u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
113 * Cannot enable ESPI interrupts on T1B because HW asserts the in t1_espi_intr_enable()
114 * interrupt incorrectly, namely the driver gets ESPI interrupts in t1_espi_intr_enable()
115 * but no data is actually dropped (can verify this reading the ESPI in t1_espi_intr_enable()
116 * drop registers). Also, once the ESPI interrupt is asserted it in t1_espi_intr_enable()
119 enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK; in t1_espi_intr_enable()
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| H A D | espi.h | 4 * File: espi.h *
46 void t1_espi_destroy(struct peespi *espi);
47 int t1_espi_init(struct peespi *espi, int mac_type, int nports);
53 const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi);
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| H A D | subr.c | 37 #include "espi.h"
766 if (adapter->espi) { in t1_interrupts_enable()
768 t1_espi_intr_enable(adapter->espi); in t1_interrupts_enable()
798 if (adapter->espi) in t1_interrupts_disable()
799 t1_espi_intr_disable(adapter->espi); in t1_interrupts_disable()
824 if (adapter->espi) in t1_interrupts_clear()
825 t1_espi_intr_clear(adapter->espi); in t1_interrupts_clear()
863 t1_espi_intr_handler(adapter->espi); in asic_slow_intr()
992 if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac, in t1_init_hw_modules()
1043 if (adapter->espi) in t1_free_sw_modules()
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| /openbmc/u-boot/drivers/spi/ |
| H A D | fsl_espi.c | 3 * eSPI controller driver.
17 ccsr_espi_t *espi; member
81 fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); in spi_setup_slave()
85 /* Set eSPI BRG clock source */ in spi_setup_slave()
108 /* set tx_timeout to 10 times of one espi FIFO entry go out */ in spi_setup_slave()
124 ccsr_espi_t *espi = fsl->espi; in spi_claim_bus() local
133 /* Enable eSPI interface */ in spi_claim_bus()
134 out_be32(&espi->mode, ESPI_MODE_RXTHR(3) in spi_claim_bus()
137 out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ in spi_claim_bus()
138 out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ in spi_claim_bus()
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| /openbmc/openbmc/meta-google/recipes-google/bare-metal-espi/ |
| H A D | bare-metal-espi.bb | 1 SUMMARY = "Disable eSPI while the customer's host OS is running"
2 DESCRIPTION = "Disable eSPI while an untrusted host OS is running"
11 file://disable-espi.service \
18 espi-control \
23 disable-espi.service \
28 install -m 0644 ${UNPACKDIR}/disable-espi.service ${D}${systemd_system_unitdir}
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| /openbmc/google-misc/subprojects/espi-control/ |
| H A D | npcm7xx_espi_control.cpp | 46 /* Base address for Nuvoton's eSPI register space. */
49 * Offset of the eSPI config (ESPICFG) register, along with host channel enable
76 std::fprintf(stderr, "Enable or disable eSPI bus on NPCM7XX BMC\n"); in usage()
77 std::fprintf(stderr, "This program will enable eSPI by default, unless " in usage()
79 std::fprintf(stderr, " -d Disable eSPI\n"); in usage()
134 * Find the start of the page that includes the start of the eSPI register in modifyESPIRegisters()
154 * Check if the automatic ready bits are set in the eSPI host in modifyESPIRegisters()
183 fprintf(stderr, "Disabled eSPI bus\n"); in modifyESPIRegisters()
187 /* Enable eSPI by setting the core channel enable bits in ESPICFG. */ in modifyESPIRegisters()
191 fprintf(stderr, "Enabled eSPI bus\n"); in modifyESPIRegisters()
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | fsl-spi.txt | 39 * eSPI (Enhanced Serial Peripheral Interface)
42 - compatible : should be "fsl,mpc8536-espi".
44 - interrupts : should contain eSPI interrupt, the device has one interrupt.
45 - fsl,espi-num-chipselects : the number of the chipselect signals.
55 compatible = "fsl,mpc8536-espi";
59 fsl,espi-num-chipselects = <4>;
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| /openbmc/u-boot/doc/ |
| H A D | README.pblimage | 5 The CoreNet SoC's can boot directly from eSPI FLASH, SD/MMC and
17 For eSPI boot(available on P2041/P3041/P4080/P5020/P5040/T4240):
18 To build the eSPI boot image:
31 boot image that can be flashed on the board eSPI flash, SD/MMC and NAND.
34 1). Boot from eSPI flash
35 Write u-boot.pbl to eSPI flash from offset 0x0.
100 #Initialize eSPI controller
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| /openbmc/openbmc/meta-google/recipes-google/espi-control/ |
| H A D | espi-control_git.bb | 1 SUMMARY = "Enable and disable eSPI bus on demand"
2 DESCRIPTION = "Enable and disable eSPI bus on demand"
3 GOOGLE_MISC_PROJ = "espi-control"
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| /openbmc/openbmc/meta-google/recipes-google/bare-metal-espi/bare-metal-espi/ |
| H A D | disable-espi.service | 2 Description=Disable eSPI bus
9 ExecStart=/usr/libexec/npcm7xx-espi-control -d
10 ExecStop=/usr/libexec/npcm7xx-espi-control
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| /openbmc/u-boot/board/freescale/corenet_ds/ |
| H A D | pbi.cfg | 24 #Initialize eSPI controller, default configuration is slow for eSPI to
25 #load data, this configuration comes from u-boot eSPI driver.
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| /openbmc/u-boot/board/varisys/cyrus/ |
| H A D | pbi.cfg | 26 #Initialize eSPI controller, default configuration is slow for eSPI to
27 #load data, this configuration comes from u-boot eSPI driver.
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| /openbmc/u-boot/board/freescale/t208xqds/ |
| H A D | t208x_pbi.cfg | 25 #Initialize eSPI controller, default configuration is slow for eSPI to
26 #load data, this configuration comes from u-boot eSPI driver.
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| /openbmc/u-boot/board/freescale/t208xrdb/ |
| H A D | t2080_pbi.cfg | 25 #Initialize eSPI controller, default configuration is slow for eSPI to
26 #load data, this configuration comes from u-boot eSPI driver.
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| /openbmc/u-boot/board/aspeed/evb_ast2600/ |
| H A D | evb_ast2600.c | 77 /* skip eSPI init if LPC mode is selected */ in espi_init()
83 * Aspeed STRONGLY NOT recommend to use eSPI early init. in espi_init()
85 * This eSPI early init sequence merely set OOB_FREE. It in espi_init()
90 * when BMC firmware is ready. That is, the eSPI kernel in espi_init()
91 * driver is mounted and ready to serve eSPI. However, in espi_init()
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| /openbmc/u-boot/board/keymile/kmp204x/ |
| H A D | pbi.cfg | 65 #Initialize eSPI controller, default configuration is slow for eSPI to
66 #load data, this configuration comes from u-boot eSPI driver.
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| /openbmc/u-boot/board/aspeed/ast2600_dcscm/ |
| H A D | ast2600_dcscm.c | 77 /* skip eSPI init if LPC mode is selected */ in espi_init()
83 * Aspeed STRONGLY NOT recommend to use eSPI early init. in espi_init()
85 * This eSPI early init sequence merely set OOB_FREE. It in espi_init()
90 * when BMC firmware is ready. That is, the eSPI kernel in espi_init()
91 * driver is mounted and ready to serve eSPI. However, in espi_init()
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| /openbmc/u-boot/board/aspeed/ast2600_intel/ |
| H A D | intel.c | 22 /* eSPI registers */
173 * Aspeed STRONGLY NOT recommend to use eSPI early init. in espi_init()
175 * This eSPI early init sequence merely set OOB_FREE. It in espi_init()
180 * when BMC firmware is ready. That is, the eSPI kernel in espi_init()
181 * driver is mounted and ready to serve eSPI. However, in espi_init()
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| /openbmc/u-boot/arch/arm/mach-aspeed/ |
| H A D | Kconfig | 23 which is enabled by support of LPC and eSPI peripherals.
32 which is enabled by support of LPC and eSPI peripherals.
45 which is enabled by support of LPC and eSPI peripherals.
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| /openbmc/qemu/docs/system/arm/ |
| H A D | nuvoton.rst | 57 * LPC/eSPI host-to-BMC interface, including
64 * eSPI slave interface
73 * LPC/eSPI host
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| /openbmc/linux/arch/powerpc/boot/dts/fsl/ |
| H A D | pq3-espi-0.dtsi | 2 * PQ3 eSPI device tree stub [ controller @ offset 0x7000 ]
38 compatible = "fsl,mpc8536-espi";
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| H A D | qoriq-espi-0.dtsi | 2 * QorIQ eSPI device tree stub [ controller @ offset 0x110000 ]
38 compatible = "fsl,mpc8536-espi";
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| /openbmc/openbmc/meta-ibm/meta-system1/recipes-phosphor/flash/bios-version/ |
| H A D | bios-version.sh | 22 # Fetch the MTD device number for the specified espi flash device
23 DEVICE_NAME="espi-flash-mafs"
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