| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-exynos-audss.c | 25 * access to audss registers. Typically a child of EPLL.
29 static struct clk *epll; variable
142 epll = ERR_PTR(-ENODEV); in exynos_audss_clk_probe()
162 epll = pll_in; in exynos_audss_clk_probe()
164 ret = clk_prepare_enable(epll); in exynos_audss_clk_probe()
167 "failed to prepare the epll clock\n"); in exynos_audss_clk_probe()
264 if (!IS_ERR(epll)) in exynos_audss_clk_probe()
265 clk_disable_unprepare(epll); in exynos_audss_clk_probe()
277 if (!IS_ERR(epll)) in exynos_audss_clk_remove()
278 clk_disable_unprepare(epll); in exynos_audss_clk_remove()
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| H A D | clk-exynos5410.c | 64 apll, cpll, epll, mpll, enumerator
247 [epll] = PLL(pll_2650x, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
275 exynos5410_plls[epll].rate_table = exynos5410_pll2550x_24mhz_tbl; in exynos5410_clk_init()
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| H A D | clk-s5pv210.c | 70 epll, enumerator
720 [epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll",
732 [epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll",
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| /openbmc/u-boot/doc/device-tree-bindings/exynos/ |
| H A D | sound.txt | 8 - samsung,i2s-epll-clock-frequency : epll clock output frequency in Hz
20 samsung,i2s-epll-clock-frequency = <192000000>;
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| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 101 /* Epll Clock division values to achive different frequency output */
140 if (pllreg == EPLL || pllreg == RPLL) { in exynos_get_pll_clk()
198 case EPLL: in exynos4_get_pll_clk()
228 case EPLL: in exynos4x12_get_pll_clk()
259 case EPLL: in exynos5_get_pll_clk()
317 case EPLL: in exynos542x_get_pll_clk()
440 sclk = exynos5_get_pll_clk(EPLL); in exynos5_get_periph_rate()
534 sclk = exynos542x_get_pll_clk(EPLL); in exynos542x_get_periph_rate()
654 sclk = get_pll_clk(EPLL); in exynos4_get_pwm_clk()
715 sclk = get_pll_clk(EPLL); in exynos4_get_uart_clk()
[all …]
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| H A D | clock_init_exynos5.c | 151 /* EPLL @600MHz */
653 /* Set EPLL */ in exynos5250_system_clock_init()
860 /* Set EPLL */ in exynos5420_system_clock_init()
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| /openbmc/u-boot/drivers/sound/ |
| H A D | samsung-i2s.c | 306 /* Set EPLL Clock */ in i2s_tx_init()
312 /* Set EPLL Clock */ in i2s_tx_init()
320 debug("%s: epll clock set rate failed\n", __func__); in i2s_tx_init()
405 if (dev_read_u32u(dev, "samsung,i2s-epll-clock-frequency", in samsung_i2s_ofdata_to_platdata()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | exynos5250.dtsi | 87 samsung,i2s-epll-clock-frequency = <192000000>;
101 samsung,i2s-epll-clock-frequency = <192000000>;
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| H A D | exynos54xx.dtsi | 112 samsung,i2s-epll-clock-frequency = <192000000>;
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | nuvoton,ma35d1-clk.h | 23 #define EPLL 12 macro
25 /* EPLL divider */
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| /openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | clk.h | 13 #define EPLL 2 macro
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| /openbmc/linux/sound/soc/samsung/ |
| H A D | arndale.c | 73 * We add 1 to the frequency value to ensure proper EPLL setting in arndale_wm1811_hw_params()
75 * samsung/clk-exynos5250.c for list of available EPLL rates). in arndale_wm1811_hw_params()
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| /openbmc/linux/arch/arm64/boot/dts/nuvoton/ |
| H A D | ma35d1-iot-512m.dts | 44 <&clk EPLL>,
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| H A D | ma35d1-som-256m.dts | 44 <&clk EPLL>,
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | nuvoton,ma35d1-clk.yaml | 37 EPLL, and VPLL in sequential.
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| /openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | clk.h | 12 #define EPLL 2 macro
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| /openbmc/u-boot/arch/arm/mach-s5pc1xx/ |
| H A D | clock.c | 39 case EPLL: in s5pc100_get_pll_clk()
90 case EPLL: in s5pc110_get_pll_clk()
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| /openbmc/linux/drivers/clk/nuvoton/ |
| H A D | clk-ma35d1.c | 104 { .fw_name = "epll", },
508 hws[EPLL] = ma35d1_reg_clk_pll(dev, EPLL, pllmode[3], "epll", in ma35d1_clocks_probe()
513 hws[EPLL_DIV2] = ma35d1_clk_fixed_factor(dev, "epll_div2", "epll", 1, 2); in ma35d1_clocks_probe()
514 hws[EPLL_DIV4] = ma35d1_clk_fixed_factor(dev, "epll_div4", "epll", 1, 4); in ma35d1_clocks_probe()
515 hws[EPLL_DIV8] = ma35d1_clk_fixed_factor(dev, "epll_div8", "epll", 1, 8); in ma35d1_clocks_probe()
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| H A D | clk-ma35d1-pll.c | 237 case EPLL: in ma35d1_clk_pll_recalc_rate()
269 case EPLL: in ma35d1_clk_pll_round_rate()
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| /openbmc/u-boot/include/ |
| H A D | exynos_lcd.h | 71 /* parent clock name(MPLL, EPLL or VPLL) */
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-ast2600.c | 116 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
211 /* For hpll/dpll/epll/mpll */
475 "epll",
663 hw = clk_hw_register_divider_table(dev, "bclk", "epll", 0, in aspeed_g6_clk_probe()
770 aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val); in aspeed_g6_cc()
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| /openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | pll.c | 357 EPLL, enumerator
460 { CPM_I2SCDR, EPLL, 30 }, in pll_init()
475 pll_init_one(EPLL, JZ4780_EPLL_M, JZ4780_EPLL_N, JZ4780_EPLL_OD); in pll_init()
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| /openbmc/u-boot/doc/device-tree-bindings/video/ |
| H A D | exynos-fb.txt | 55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | s5p_sdhci.c | 66 * 10 = EPLL in s5p_sdhci_set_control_reg()
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| /openbmc/u-boot/drivers/clk/aspeed/ |
| H A D | clk_ast2600.c | 1060 * EPLL -->|/ |
1068 * 1. RGMII 1/2 always use EPLL as the internal clock source
1072 * EPLL---->| divider |--->|/ +
1181 * EPLL -->|/
1611 { ASPEED_CLK_APLL, "apll" }, { ASPEED_CLK_EPLL, "epll" },
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