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Searched full:enci (Results 1 – 15 of 15) sorted by relevance

/openbmc/u-boot/drivers/video/meson/
H A Dmeson_venc.c118 } enci; member
173 .enci = {
193 .enci = {
864 writel(vmode->enci.hso_begin, in meson_venc_hdmi_mode_set()
866 writel(vmode->enci.hso_end, in meson_venc_hdmi_mode_set()
870 writel(vmode->enci.vso_even, in meson_venc_hdmi_mode_set()
872 writel(vmode->enci.vso_odd, in meson_venc_hdmi_mode_set()
876 writel(vmode->enci.macv_max_amp, in meson_venc_hdmi_mode_set()
880 writel(vmode->enci.video_prog_mode, in meson_venc_hdmi_mode_set()
882 writel(vmode->enci.video_mode, in meson_venc_hdmi_mode_set()
[all …]
H A Dmeson_vclk.c201 * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
258 /* select vclk_div1 for enci */ in meson_venci_cvbs_clock_config()
708 /* Set ENCI/ENCP Source */ in meson_vclk_set()
716 /* select vclk_div1 for enci */ in meson_vclk_set()
730 /* select vclk_div2 for enci */ in meson_vclk_set()
746 /* select vclk_div4 for enci */ in meson_vclk_set()
762 /* select vclk_div6 for enci */ in meson_vclk_set()
778 /* select vclk_div12 for enci */ in meson_vclk_set()
791 /* Enable ENCI clock gate */ in meson_vclk_set()
H A Dmeson_vpu.h82 /* Mux VIU/VPP to ENCI */
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_venc.c25 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
40 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
47 * The ENCI is designed for PAl or NTSC encoding and can go through the VDAC
55 * The ENCI and ENCP encoders needs specially defined parameters for each
58 * The ENCI end ENCP DVI encoders are more generic and can generate any timings
59 * from the pixel data generated by ENCI or ENCP, so can use the standard video
137 } enci; member
192 .enci = {
212 .enci = {
1070 writel_relaxed(vmode->enci.hso_begin, in meson_venc_hdmi_mode_set()
[all …]
H A Dmeson_encoder_cvbs.c47 .enci = &meson_cvbs_enci_pal,
56 .enci = &meson_cvbs_enci_ntsc,
168 meson_venci_cvbs_mode_set(priv, meson_mode->enci); in meson_encoder_cvbs_atomic_enable()
170 /* Setup 27MHz vclk2 for ENCI and VDAC */ in meson_encoder_cvbs_atomic_enable()
H A Dmeson_vclk.c33 * | | | | | |--ENCI
236 * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
313 /* select vclk_div1 for enci */ in meson_venci_cvbs_clock_config()
941 /* Set ENCI/ENCP Source */ in meson_vclk_set()
949 /* select vclk_div1 for enci */ in meson_vclk_set()
963 /* select vclk_div2 for enci */ in meson_vclk_set()
977 /* select vclk_div4 for enci */ in meson_vclk_set()
991 /* select vclk_div6 for enci */ in meson_vclk_set()
1005 /* select vclk_div12 for enci */ in meson_vclk_set()
1016 /* Enable ENCI clock gate */ in meson_vclk_set()
H A Dmeson_encoder_cvbs.h18 struct meson_cvbs_enci_mode *enci; member
H A Dmeson_vpp.h17 /* Mux VIU/VPP to ENCI */
H A Dmeson_venc.h9 * - ENCI : Interlace Video Encoder
H A Dmeson_dw_hdmi.c65 * block and the VPU HDMI mux selects either the ENCI
69 * The VENC uses a DVI encoder on top of the ENCI
H A Dmeson_encoder_hdmi.c110 dev_dbg(priv->dev, "vclk:%d phy=%d venc=%d hdmi=%d enci=%d\n", in meson_encoder_hdmi_set_vclk()
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Damlogic,meson-vpu.yaml22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
50 - ENCI : Interlace Video encoder for CVBS and Interlace HDMI
55 The ENCI is connected to a single VDAC for Composite Output.
56 The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
H A Damlogic,meson-dw-hdmi.yaml37 selects either the ENCI encoder for the 576i or 480i formats or the ENCP
40 The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
/openbmc/linux/Documentation/gpu/
H A Dmeson.rst21 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
/openbmc/linux/drivers/soc/amlogic/
H A Dmeson-clk-measure.c107 CLK_MSR_ID(6, "enci"),
251 CLK_MSR_ID(6, "enci"),
368 CLK_MSR_ID(6, "enci"),