| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | qcom,dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5332-dwc3
18 - qcom,ipq6018-dwc3
19 - qcom,ipq8064-dwc3
20 - qcom,ipq8074-dwc3
21 - qcom,ipq9574-dwc3
22 - qcom,msm8953-dwc3
23 - qcom,msm8994-dwc3
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| H A D | dwc3-st.txt | 1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
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| H A D | rockchip,dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
7 title: Rockchip SuperSpeed DWC3 USB SoC controller
13 The common content of the node is defined in snps,dwc3.yaml.
24 - $ref: snps,dwc3.yaml#
31 - rockchip,rk3328-dwc3
32 - rockchip,rk3568-dwc3
40 - rockchip,rk3328-dwc3
41 - rockchip,rk3568-dwc3
42 - const: snps,dwc3
99 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
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| H A D | omap-usb.txt | 46 OMAP DWC3 GLUE
48 * "ti,dwc3" for OMAP5 and DRA7
49 * "ti,am437x-dwc3" for AM437x
60 - extcon : phandle for the extcon device omap dwc3 uses to detect
65 The dwc3 core should be added as subnode to omap dwc3 glue.
66 - dwc3 :
67 The binding details of dwc3 can be found in:
68 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
71 compatible = "ti,dwc3";
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| H A D | fsl,imx8mq-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/fsl,imx8mq-dwc3.yaml#
18 - fsl,imx8mq-dwc3
25 - const: fsl,imx8mq-dwc3
26 - const: snps,dwc3
29 - $ref: snps,dwc3.yaml#
39 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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| H A D | ti,keystone-dwc3.yaml | 4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
61 $ref: snps,dwc3.yaml#
77 dwc3@2680000 {
78 compatible = "ti,keystone-dwc3";
87 compatible = "snps,dwc3";
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| /openbmc/linux/drivers/usb/dwc3/ |
| H A D | Makefile | 5 obj-$(CONFIG_USB_DWC3) += dwc3.o
7 dwc3-y := core.o
10 dwc3-y += trace.o
14 dwc3-y += host.o
18 dwc3-y += gadget.o ep0.o
22 dwc3-y += drd.o
26 dwc3-y += ulpi.o
30 dwc3-y += debugfs.o
45 obj-$(CONFIG_USB_DWC3_AM62) += dwc3-am62.o
46 obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
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| H A D | dwc3-haps.c | 3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
20 * @dwc3: child dwc3 platform_device
24 struct platform_device *dwc3; member
60 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
61 if (!dwc->dwc3) in dwc3_haps_probe()
75 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
77 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe()
82 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
84 ret = device_add_software_node(&dwc->dwc3->dev, &dwc3_haps_swnode); in dwc3_haps_probe()
88 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
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| H A D | dwc3-imx8mp.c | 3 * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
53 struct platform_device *dwc3; member
101 struct dwc3 *dwc3 = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_wakeup_enable() local
104 if (!dwc3) in dwc3_imx8mp_wakeup_enable()
109 if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci) in dwc3_imx8mp_wakeup_enable()
112 else if (dwc3->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) in dwc3_imx8mp_wakeup_enable()
131 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_interrupt()
222 dwc3_np = of_get_compatible_child(node, "snps,dwc3"); in dwc3_imx8mp_probe()
225 dev_err(dev, "failed to find dwc3 core child\n"); in dwc3_imx8mp_probe()
231 dev_err(&pdev->dev, "failed to create dwc3 core\n"); in dwc3_imx8mp_probe()
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| H A D | dwc3-pci.c | 3 * dwc3-pci.c - PCI Specific glue layer
74 * @dwc3: child dwc3 platform_device
81 struct platform_device *dwc3; member
273 * Make the pdev name predictable (only 1 DWC3 on BYT) in dwc3_pci_quirks()
277 dwc->dwc3->id = PLATFORM_DEVID_NONE; in dwc3_pci_quirks()
278 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; in dwc3_pci_quirks()
298 return device_add_software_node(&dwc->dwc3->dev, swnode); in dwc3_pci_quirks()
305 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local
308 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work()
310 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
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| H A D | dwc3-qcom.c | 4 * Inspired by dwc3-of-simple.c
70 struct platform_device *dwc3; member
267 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev); in dwc3_qcom_interconnect_init()
310 struct dwc3 *dwc; in dwc3_qcom_is_host()
315 dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_is_host()
326 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in dwc3_qcom_read_usb2_speed()
337 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code in dwc3_qcom_read_usb2_speed()
489 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); in qcom_dwc3_resume_irq()
507 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ in dwc3_qcom_select_utmi_clk()
675 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_qcom_acpi_register_core()
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| H A D | core.c | 49 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode()
92 !DWC3_VER_IS_PRIOR(DWC3, 330A)) in dwc3_get_dr_mode()
107 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) in dwc3_enable_susphy()
128 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) in dwc3_set_prtcap()
142 struct dwc3 *dwc = work_to_dwc(work); in __dwc3_set_mode()
190 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || in __dwc3_set_mode()
261 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) in dwc3_set_mode()
277 struct dwc3 *dwc = dep->dwc; in dwc3_core_fifo_space()
293 int dwc3_core_soft_reset(struct dwc3 *dwc) in dwc3_core_soft_reset()
300 * XHCI driver will reset the host block. If dwc3 was configured for in dwc3_core_soft_reset()
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| H A D | drd.c | 19 static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask) in dwc3_otg_disable_events()
27 static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask) in dwc3_otg_enable_events()
35 static void dwc3_otg_clear_events(struct dwc3 *dwc) in dwc3_otg_clear_events()
54 struct dwc3 *dwc = _dwc; in dwc3_otg_thread_irq()
72 struct dwc3 *dwc = _dwc; in dwc3_otg_irq()
93 static void dwc3_otgregs_init(struct dwc3 *dwc) in dwc3_otgregs_init()
137 static int dwc3_otg_get_irq(struct dwc3 *dwc) in dwc3_otg_get_irq()
167 void dwc3_otg_init(struct dwc3 *dwc) in dwc3_otg_init()
186 void dwc3_otg_exit(struct dwc3 *dwc) in dwc3_otg_exit()
195 void dwc3_otg_host_init(struct dwc3 *dwc) in dwc3_otg_host_init()
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| H A D | ep0.c | 30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
33 static int dwc3_ep0_delegate_req(struct dwc3 *dwc,
40 struct dwc3 *dwc; in dwc3_ep0_prepare_one_trb()
68 struct dwc3 *dwc; in dwc3_ep0_start_trans()
92 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_queue()
195 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_queue()
223 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) in dwc3_ep0_stall_and_restart()
258 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_set_halt()
268 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_set_halt()
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| H A D | gadget.c | 41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) in dwc3_gadget_set_test_mode()
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc) in dwc3_gadget_get_link_state()
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) in dwc3_gadget_set_link_state()
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { in dwc3_gadget_set_link_state()
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) in dwc3_gadget_set_link_state()
142 static void dwc3_ep0_reset_state(struct dwc3 *dwc) in dwc3_ep0_reset_state()
196 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_del_and_unmap_request()
230 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_giveback()
249 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, in dwc3_send_gadget_generic_command()
280 static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async);
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| H A D | core.h | 77 /* DWC3 registers memory space boundries */
688 struct dwc3 *dwc;
736 struct dwc3 *dwc;
929 * @status: internal dwc3 request status tracking
979 * struct dwc3 - representation of our controller
1071 * @sysdev_is_parent: true when dwc3 device has a parent driver
1079 * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
1142 struct dwc3 { struct
1370 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) argument
1521 * DWC3 Features to be used as Driver Data
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| /openbmc/u-boot/drivers/usb/dwc3/ |
| H A D | dwc3-generic.c | 3 * Generic DWC3 Glue layer
7 * Based on dwc3-omap.c.
15 #include <dwc3-uboot.h>
27 struct dwc3 dwc3; member
36 struct dwc3 *dwc3 = &priv->dwc3; in dm_usb_gadget_handle_interrupts() local
38 dwc3_gadget_uboot_handle_interrupt(dwc3); in dm_usb_gadget_handle_interrupts()
47 struct dwc3 *dwc3 = &priv->dwc3; in dwc3_generic_peripheral_probe() local
53 dwc3->regs = map_physmem(priv->base, DWC3_OTG_REGS_END, MAP_NOCACHE); in dwc3_generic_peripheral_probe()
54 dwc3->regs += DWC3_GLOBALS_REGS_START; in dwc3_generic_peripheral_probe()
55 dwc3->dev = dev; in dwc3_generic_peripheral_probe()
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| H A D | core.c | 10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
13 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
18 #include <dwc3-uboot.h>
35 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) in dwc3_set_mode()
49 static int dwc3_core_soft_reset(struct dwc3 *dwc) in dwc3_core_soft_reset()
95 static void dwc3_free_one_event_buffer(struct dwc3 *dwc, in dwc3_free_one_event_buffer()
109 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, in dwc3_alloc_one_event_buffer()
135 static void dwc3_free_event_buffers(struct dwc3 *dwc) in dwc3_free_event_buffers()
155 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) in dwc3_alloc_event_buffers()
188 static int dwc3_event_buffers_setup(struct dwc3 *dwc) in dwc3_event_buffers_setup()
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| H A D | Makefile | 3 obj-$(CONFIG_USB_DWC3) += dwc3.o
5 dwc3-y := core.o
9 obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
10 obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o
11 obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o
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| H A D | dwc3-uniphier.c | 3 * UniPhier Specific Glue Layer for DWC3
92 .compatible = "socionext,uniphier-pro4-dwc3",
96 .compatible = "socionext,uniphier-pro5-dwc3",
100 .compatible = "socionext,uniphier-pxs2-dwc3",
104 .compatible = "socionext,uniphier-ld20-dwc3",
108 .compatible = "socionext,uniphier-pxs3-dwc3",
115 .name = "uniphier-dwc3",
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| /openbmc/u-boot/doc/device-tree-bindings/usb/ |
| H A D | dwc3-st.txt | 1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
28 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
32 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are
37 st_dwc3: dwc3@8f94000 {
39 compatible = "st,stih407-dwc3";
52 dwc3: dwc3@9900000 {
53 compatible = "snps,dwc3";
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| /openbmc/u-boot/drivers/usb/host/ |
| H A D | xhci-dwc3.c | 5 * DWC3 controller driver
15 #include <dwc3-uboot.h>
19 #include <linux/usb/dwc3.h>
27 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) in dwc3_set_mode()
34 static void dwc3_phy_reset(struct dwc3 *dwc3_reg) in dwc3_phy_reset()
51 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) in dwc3_core_soft_reset()
65 int dwc3_core_init(struct dwc3 *dwc3_reg) in dwc3_core_init()
94 * WORKAROUND: DWC3 revisions <1.90a have a bug in dwc3_core_init()
107 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val) in dwc3_set_fladj()
118 struct dwc3 *dwc3_reg; in xhci_dwc3_probe()
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| H A D | dwc3-sti-glue.c | 3 * STiH407 family DWC3 specific Glue layer
21 #include <linux/usb/dwc3.h>
23 #include <dwc3-sti-glue.h>
28 * struct sti_dwc3_glue_platdata - dwc3 STi glue driver private structure
115 pr_err("unable to find st,stih407-dwc3 reg property(%d)\n", ret); in sti_dwc3_glue_ofdata_to_platdata()
165 /* check if the subnode compatible string is the dwc3 one*/ in sti_dwc3_glue_bind()
167 "snps,dwc3") != 0) { in sti_dwc3_glue_bind()
168 pr_err("Can't find dwc3 subnode for %s\n", dev->name); in sti_dwc3_glue_bind()
172 /* retrieve the DWC3 dual role mode */ in sti_dwc3_glue_bind()
189 pr_err("DWC3 powerdown reset deassert failed: %d", ret); in sti_dwc3_glue_probe()
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| /openbmc/linux/Documentation/devicetree/bindings/soc/socionext/ |
| H A D | socionext,uniphier-dwc3-glue.yaml | 4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
14 a sideband logic handling signals to DWC3 host controller inside
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
23 - socionext,uniphier-pxs2-dwc3-glue
24 - socionext,uniphier-ld20-dwc3-glue
25 - socionext,uniphier-pxs3-dwc3-glue
26 - socionext,uniphier-nx1-dwc3-glue
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| /openbmc/qemu/hw/usb/ |
| H A D | xlnx-usb-subsystem.c | 40 sysbus_realize(SYS_BUS_DEVICE(&s->dwc3), &err); in versal_usb2_realize()
52 qdev_pass_gpios(DEVICE(&s->dwc3.sysbus_xhci), dev, SYSBUS_DEVICE_GPIO_IRQ); in versal_usb2_realize()
59 object_initialize_child(obj, "versal.dwc3", &s->dwc3, in versal_usb2_init()
64 &s->dwc3.iomem, 0, DWC3_SIZE); in versal_usb2_init()
67 qdev_alias_all_properties(DEVICE(&s->dwc3), obj); in versal_usb2_init()
68 qdev_alias_all_properties(DEVICE(&s->dwc3.sysbus_xhci), obj); in versal_usb2_init()
69 object_property_add_alias(obj, "dma", OBJECT(&s->dwc3.sysbus_xhci), "dma"); in versal_usb2_init()
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