15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0
2cbdc0f54SMauro Carvalho Chehab /*
372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file
472246da4SFelipe Balbi *
510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
672246da4SFelipe Balbi *
772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>,
872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
972246da4SFelipe Balbi */
1072246da4SFelipe Balbi
11fe8abf33SMasahiro Yamada #include <linux/clk.h>
12fa0ea13eSFelipe Balbi #include <linux/version.h>
13a72e658bSFelipe Balbi #include <linux/module.h>
1472246da4SFelipe Balbi #include <linux/kernel.h>
1572246da4SFelipe Balbi #include <linux/slab.h>
1672246da4SFelipe Balbi #include <linux/spinlock.h>
1772246da4SFelipe Balbi #include <linux/platform_device.h>
1872246da4SFelipe Balbi #include <linux/pm_runtime.h>
1972246da4SFelipe Balbi #include <linux/interrupt.h>
2072246da4SFelipe Balbi #include <linux/ioport.h>
2172246da4SFelipe Balbi #include <linux/io.h>
2272246da4SFelipe Balbi #include <linux/list.h>
2372246da4SFelipe Balbi #include <linux/delay.h>
2472246da4SFelipe Balbi #include <linux/dma-mapping.h>
25457e84b6SFelipe Balbi #include <linux/of.h>
26d182c2e1SAndrey Smirnov #include <linux/of_graph.h>
27404905a6SHeikki Krogerus #include <linux/acpi.h>
286344475fSSekhar Nori #include <linux/pinctrl/consumer.h>
29fe8abf33SMasahiro Yamada #include <linux/reset.h>
307bee3188SBalaji Prakash J #include <linux/bitfield.h>
3172246da4SFelipe Balbi
3272246da4SFelipe Balbi #include <linux/usb/ch9.h>
3372246da4SFelipe Balbi #include <linux/usb/gadget.h>
34f7e846f0SFelipe Balbi #include <linux/usb/of.h>
35a45c82b8SRuchika Kharwar #include <linux/usb/otg.h>
3672246da4SFelipe Balbi
3772246da4SFelipe Balbi #include "core.h"
3872246da4SFelipe Balbi #include "gadget.h"
3972246da4SFelipe Balbi #include "io.h"
4072246da4SFelipe Balbi
4172246da4SFelipe Balbi #include "debug.h"
4272246da4SFelipe Balbi
43fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
448300dd23SFelipe Balbi
459d6173e1SThinh Nguyen /**
469d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode
479d6173e1SThinh Nguyen * @dwc: pointer to our context structure
489d6173e1SThinh Nguyen */
dwc3_get_dr_mode(struct dwc3 * dwc)499d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc)
509d6173e1SThinh Nguyen {
519d6173e1SThinh Nguyen enum usb_dr_mode mode;
529d6173e1SThinh Nguyen struct device *dev = dwc->dev;
539d6173e1SThinh Nguyen unsigned int hw_mode;
549d6173e1SThinh Nguyen
559d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
569d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG;
579d6173e1SThinh Nguyen
589d6173e1SThinh Nguyen mode = dwc->dr_mode;
599d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
609d6173e1SThinh Nguyen
619d6173e1SThinh Nguyen switch (hw_mode) {
629d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET:
639d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
649d6173e1SThinh Nguyen dev_err(dev,
659d6173e1SThinh Nguyen "Controller does not support host mode.\n");
669d6173e1SThinh Nguyen return -EINVAL;
679d6173e1SThinh Nguyen }
689d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL;
699d6173e1SThinh Nguyen break;
709d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST:
719d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
729d6173e1SThinh Nguyen dev_err(dev,
739d6173e1SThinh Nguyen "Controller does not support device mode.\n");
749d6173e1SThinh Nguyen return -EINVAL;
759d6173e1SThinh Nguyen }
769d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST;
779d6173e1SThinh Nguyen break;
789d6173e1SThinh Nguyen default:
799d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
809d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST;
819d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
829d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL;
83a7700468SThinh Nguyen
84a7700468SThinh Nguyen /*
8589a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
8689a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not
8789a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral.
88a7700468SThinh Nguyen */
89d182c2e1SAndrey Smirnov if (mode == USB_DR_MODE_OTG && !dwc->edev &&
908bb14308SThinh Nguyen (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
918bb14308SThinh Nguyen !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
929af21dd6SThinh Nguyen !DWC3_VER_IS_PRIOR(DWC3, 330A))
93a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL;
949d6173e1SThinh Nguyen }
959d6173e1SThinh Nguyen
969d6173e1SThinh Nguyen if (mode != dwc->dr_mode) {
979d6173e1SThinh Nguyen dev_warn(dev,
989d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n",
999d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget");
1009d6173e1SThinh Nguyen
1019d6173e1SThinh Nguyen dwc->dr_mode = mode;
1029d6173e1SThinh Nguyen }
1039d6173e1SThinh Nguyen
1049d6173e1SThinh Nguyen return 0;
1059d6173e1SThinh Nguyen }
1069d6173e1SThinh Nguyen
dwc3_enable_susphy(struct dwc3 * dwc,bool enable)107000f9944SThinh Nguyen void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
108000f9944SThinh Nguyen {
109000f9944SThinh Nguyen u32 reg;
110000f9944SThinh Nguyen
111000f9944SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
112000f9944SThinh Nguyen if (enable && !dwc->dis_u3_susphy_quirk)
113000f9944SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY;
114000f9944SThinh Nguyen else
115000f9944SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
116000f9944SThinh Nguyen
117000f9944SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
118000f9944SThinh Nguyen
119000f9944SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
120000f9944SThinh Nguyen if (enable && !dwc->dis_u2_susphy_quirk)
121000f9944SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY;
122000f9944SThinh Nguyen else
123000f9944SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
124000f9944SThinh Nguyen
125000f9944SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
126000f9944SThinh Nguyen }
127000f9944SThinh Nguyen
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)128f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
1293140e8cbSSebastian Andrzej Siewior {
1303140e8cbSSebastian Andrzej Siewior u32 reg;
1313140e8cbSSebastian Andrzej Siewior
1323140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1333140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
1343140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode);
1353140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg);
136c4a5153eSManu Gautam
137c4a5153eSManu Gautam dwc->current_dr_role = mode;
13841ce1456SRoger Quadros }
1396b3261a2SRoger Quadros
__dwc3_set_mode(struct work_struct * work)14041ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work)
14141ce1456SRoger Quadros {
14241ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work);
14341ce1456SRoger Quadros unsigned long flags;
14441ce1456SRoger Quadros int ret;
145f580170fSYu Chen u32 reg;
14662c73bfeSSven Peter u32 desired_dr_role;
14741ce1456SRoger Quadros
148f88359e1SYu Chen mutex_lock(&dwc->mutex);
14962c73bfeSSven Peter spin_lock_irqsave(&dwc->lock, flags);
15062c73bfeSSven Peter desired_dr_role = dwc->desired_dr_role;
15162c73bfeSSven Peter spin_unlock_irqrestore(&dwc->lock, flags);
152f88359e1SYu Chen
153c2cd3452SMartin Kepplinger pm_runtime_get_sync(dwc->dev);
154c2cd3452SMartin Kepplinger
155f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
156f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0);
157f09cc79bSRoger Quadros
15862c73bfeSSven Peter if (!desired_dr_role)
159c2cd3452SMartin Kepplinger goto out;
16041ce1456SRoger Quadros
16162c73bfeSSven Peter if (desired_dr_role == dwc->current_dr_role)
162c2cd3452SMartin Kepplinger goto out;
16341ce1456SRoger Quadros
16462c73bfeSSven Peter if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
165c2cd3452SMartin Kepplinger goto out;
16641ce1456SRoger Quadros
16741ce1456SRoger Quadros switch (dwc->current_dr_role) {
16841ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST:
16941ce1456SRoger Quadros dwc3_host_exit(dwc);
17041ce1456SRoger Quadros break;
17141ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE:
17241ce1456SRoger Quadros dwc3_gadget_exit(dwc);
17341ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc);
17441ce1456SRoger Quadros break;
175f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG:
176f09cc79bSRoger Quadros dwc3_otg_exit(dwc);
177f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags);
178f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
179f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags);
180f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1);
181f09cc79bSRoger Quadros break;
18241ce1456SRoger Quadros default:
18341ce1456SRoger Quadros break;
18441ce1456SRoger Quadros }
18541ce1456SRoger Quadros
18607903626SRohith Kollalsi /*
18707903626SRohith Kollalsi * When current_dr_role is not set, there's no role switching.
18807903626SRohith Kollalsi * Only perform GCTL.CoreSoftReset when there's DRD role switching.
18907903626SRohith Kollalsi */
19007903626SRohith Kollalsi if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
19107903626SRohith Kollalsi DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
19262c73bfeSSven Peter desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
193f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL);
194f88359e1SYu Chen reg |= DWC3_GCTL_CORESOFTRESET;
195f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg);
196f88359e1SYu Chen
197f88359e1SYu Chen /*
198f88359e1SYu Chen * Wait for internal clocks to synchronized. DWC_usb31 and
199f88359e1SYu Chen * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
200f88359e1SYu Chen * keep it consistent across different IPs, let's wait up to
201f88359e1SYu Chen * 100ms before clearing GCTL.CORESOFTRESET.
202f88359e1SYu Chen */
203f88359e1SYu Chen msleep(100);
204f88359e1SYu Chen
205f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL);
206f88359e1SYu Chen reg &= ~DWC3_GCTL_CORESOFTRESET;
207f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg);
208f88359e1SYu Chen }
209f88359e1SYu Chen
21041ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags);
21141ce1456SRoger Quadros
21262c73bfeSSven Peter dwc3_set_prtcap(dwc, desired_dr_role);
21341ce1456SRoger Quadros
21441ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags);
21541ce1456SRoger Quadros
21662c73bfeSSven Peter switch (desired_dr_role) {
21741ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST:
21841ce1456SRoger Quadros ret = dwc3_host_init(dwc);
219958d1a4cSFelipe Balbi if (ret) {
22041ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n");
221958d1a4cSFelipe Balbi } else {
222958d1a4cSFelipe Balbi if (dwc->usb2_phy)
223958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true);
224958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
225644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
226f580170fSYu Chen if (dwc->dis_split_quirk) {
227f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
228f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE;
229f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
230f580170fSYu Chen }
231958d1a4cSFelipe Balbi }
23241ce1456SRoger Quadros break;
23341ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE:
234f88359e1SYu Chen dwc3_core_soft_reset(dwc);
235f88359e1SYu Chen
23641ce1456SRoger Quadros dwc3_event_buffers_setup(dwc);
237958d1a4cSFelipe Balbi
238958d1a4cSFelipe Balbi if (dwc->usb2_phy)
239958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false);
240958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
241644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
242958d1a4cSFelipe Balbi
24341ce1456SRoger Quadros ret = dwc3_gadget_init(dwc);
24441ce1456SRoger Quadros if (ret)
24541ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n");
24641ce1456SRoger Quadros break;
247f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG:
248f09cc79bSRoger Quadros dwc3_otg_init(dwc);
249f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0);
250f09cc79bSRoger Quadros break;
25141ce1456SRoger Quadros default:
25241ce1456SRoger Quadros break;
25341ce1456SRoger Quadros }
254f09cc79bSRoger Quadros
255c2cd3452SMartin Kepplinger out:
256c2cd3452SMartin Kepplinger pm_runtime_mark_last_busy(dwc->dev);
257c2cd3452SMartin Kepplinger pm_runtime_put_autosuspend(dwc->dev);
258f88359e1SYu Chen mutex_unlock(&dwc->mutex);
25941ce1456SRoger Quadros }
26041ce1456SRoger Quadros
dwc3_set_mode(struct dwc3 * dwc,u32 mode)26141ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
26241ce1456SRoger Quadros {
26341ce1456SRoger Quadros unsigned long flags;
26441ce1456SRoger Quadros
265dc336b19SLi Jun if (dwc->dr_mode != USB_DR_MODE_OTG)
266dc336b19SLi Jun return;
267dc336b19SLi Jun
26841ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags);
26941ce1456SRoger Quadros dwc->desired_dr_role = mode;
27041ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags);
27141ce1456SRoger Quadros
272084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work);
2733140e8cbSSebastian Andrzej Siewior }
2748300dd23SFelipe Balbi
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)275cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
276cf6d867dSFelipe Balbi {
277cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc;
278cf6d867dSFelipe Balbi u32 reg;
279cf6d867dSFelipe Balbi
280cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
281cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) |
282cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type));
283cf6d867dSFelipe Balbi
284cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
285cf6d867dSFelipe Balbi
286cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
287cf6d867dSFelipe Balbi }
288cf6d867dSFelipe Balbi
28972246da4SFelipe Balbi /**
29072246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset
29172246da4SFelipe Balbi * @dwc: pointer to our context structure
29272246da4SFelipe Balbi */
dwc3_core_soft_reset(struct dwc3 * dwc)2930066472dSWesley Cheng int dwc3_core_soft_reset(struct dwc3 *dwc)
29472246da4SFelipe Balbi {
29572246da4SFelipe Balbi u32 reg;
296f59dcab1SFelipe Balbi int retries = 1000;
29772246da4SFelipe Balbi
298f59dcab1SFelipe Balbi /*
299f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode,
300f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for
30161a06c5bSThinh Nguyen * host-only mode, then we can return early.
302f59dcab1SFelipe Balbi */
30361a06c5bSThinh Nguyen if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
30457303488SKishon Vijay Abraham I return 0;
305f59dcab1SFelipe Balbi
306f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL);
307f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST;
308f4fd84aeSThinh Nguyen reg &= ~DWC3_DCTL_RUN_STOP;
309f4fd84aeSThinh Nguyen dwc3_gadget_dctl_write_safe(dwc, reg);
310f59dcab1SFelipe Balbi
3114749e0e6SThinh Nguyen /*
3124749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
3134749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can
3144749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms
3154749e0e6SThinh Nguyen * for 10 times instead.
3164749e0e6SThinh Nguyen */
3179af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
3184749e0e6SThinh Nguyen retries = 10;
3194749e0e6SThinh Nguyen
320f59dcab1SFelipe Balbi do {
321f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL);
322f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST))
323fab38333SThinh Nguyen goto done;
324f59dcab1SFelipe Balbi
3259af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
3264749e0e6SThinh Nguyen msleep(20);
3274749e0e6SThinh Nguyen else
328f59dcab1SFelipe Balbi udelay(1);
329f59dcab1SFelipe Balbi } while (--retries);
330f59dcab1SFelipe Balbi
331859bdc35SMayank Rana dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
332f59dcab1SFelipe Balbi return -ETIMEDOUT;
333fab38333SThinh Nguyen
334fab38333SThinh Nguyen done:
335fab38333SThinh Nguyen /*
3364749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
3374749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY
3384749e0e6SThinh Nguyen * domain (synchronization delay).
339fab38333SThinh Nguyen */
3409af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
341fab38333SThinh Nguyen msleep(50);
342fab38333SThinh Nguyen
343fab38333SThinh Nguyen return 0;
34472246da4SFelipe Balbi }
34572246da4SFelipe Balbi
346db2be4e9SNikhil Badola /*
347db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required
348db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure
349db2be4e9SNikhil Badola */
dwc3_frame_length_adjustment(struct dwc3 * dwc)350bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
351db2be4e9SNikhil Badola {
352db2be4e9SNikhil Badola u32 reg;
353db2be4e9SNikhil Badola u32 dft;
354db2be4e9SNikhil Badola
3559af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 250A))
356db2be4e9SNikhil Badola return;
357db2be4e9SNikhil Badola
358bcdb3272SFelipe Balbi if (dwc->fladj == 0)
359db2be4e9SNikhil Badola return;
360db2be4e9SNikhil Badola
361db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
362db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK;
363a7d9874cSYinbo Zhu if (dft != dwc->fladj) {
364db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK;
365bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
366db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
367db2be4e9SNikhil Badola }
368db2be4e9SNikhil Badola }
369db2be4e9SNikhil Badola
370c5cc74e8SHeikki Krogerus /**
3717bee3188SBalaji Prakash J * dwc3_ref_clk_period - Reference clock period configuration
3727bee3188SBalaji Prakash J * Default reference clock period depends on hardware
3737bee3188SBalaji Prakash J * configuration. For systems with reference clock that differs
3747bee3188SBalaji Prakash J * from the default, this will set clock period in DWC3_GUCTL
3757bee3188SBalaji Prakash J * register.
3767bee3188SBalaji Prakash J * @dwc: Pointer to our controller context structure
3777bee3188SBalaji Prakash J */
dwc3_ref_clk_period(struct dwc3 * dwc)3787bee3188SBalaji Prakash J static void dwc3_ref_clk_period(struct dwc3 *dwc)
3797bee3188SBalaji Prakash J {
3805114c3eeSSean Anderson unsigned long period;
381596c8785SSean Anderson unsigned long fladj;
382596c8785SSean Anderson unsigned long decr;
3835114c3eeSSean Anderson unsigned long rate;
3847bee3188SBalaji Prakash J u32 reg;
3857bee3188SBalaji Prakash J
3865114c3eeSSean Anderson if (dwc->ref_clk) {
3875114c3eeSSean Anderson rate = clk_get_rate(dwc->ref_clk);
3885114c3eeSSean Anderson if (!rate)
3897bee3188SBalaji Prakash J return;
3905114c3eeSSean Anderson period = NSEC_PER_SEC / rate;
3915114c3eeSSean Anderson } else if (dwc->ref_clk_per) {
3925114c3eeSSean Anderson period = dwc->ref_clk_per;
393596c8785SSean Anderson rate = NSEC_PER_SEC / period;
3945114c3eeSSean Anderson } else {
3955114c3eeSSean Anderson return;
3965114c3eeSSean Anderson }
3977bee3188SBalaji Prakash J
3987bee3188SBalaji Prakash J reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
3997bee3188SBalaji Prakash J reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
4005114c3eeSSean Anderson reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
4017bee3188SBalaji Prakash J dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
4027bee3188SBalaji Prakash J
403596c8785SSean Anderson if (DWC3_VER_IS_PRIOR(DWC3, 250A))
404596c8785SSean Anderson return;
405596c8785SSean Anderson
406596c8785SSean Anderson /*
407596c8785SSean Anderson * The calculation below is
408596c8785SSean Anderson *
409596c8785SSean Anderson * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
410596c8785SSean Anderson *
411596c8785SSean Anderson * but rearranged for fixed-point arithmetic. The division must be
412596c8785SSean Anderson * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
413596c8785SSean Anderson * neither does rate * period).
414596c8785SSean Anderson *
415596c8785SSean Anderson * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
416596c8785SSean Anderson * nanoseconds of error caused by the truncation which happened during
417596c8785SSean Anderson * the division when calculating rate or period (whichever one was
418596c8785SSean Anderson * derived from the other). We first calculate the relative error, then
419596c8785SSean Anderson * scale it to units of 8 ppm.
420596c8785SSean Anderson */
421596c8785SSean Anderson fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
422596c8785SSean Anderson fladj -= 125000;
423596c8785SSean Anderson
424596c8785SSean Anderson /*
425596c8785SSean Anderson * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
426596c8785SSean Anderson */
427596c8785SSean Anderson decr = 480000000 / rate;
428596c8785SSean Anderson
429596c8785SSean Anderson reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
430596c8785SSean Anderson reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
431596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR
432596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR_PLS1;
433596c8785SSean Anderson reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
434596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
435596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
436a6fc2f1bSAlexander Stein
437a6fc2f1bSAlexander Stein if (dwc->gfladj_refclk_lpm_sel)
438a6fc2f1bSAlexander Stein reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
439a6fc2f1bSAlexander Stein
440596c8785SSean Anderson dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
441596c8785SSean Anderson }
4427bee3188SBalaji Prakash J
4437bee3188SBalaji Prakash J /**
44472246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer
44572246da4SFelipe Balbi * @dwc: Pointer to our controller context structure
44672246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed
44772246da4SFelipe Balbi */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)44872246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
44972246da4SFelipe Balbi struct dwc3_event_buffer *evt)
45072246da4SFelipe Balbi {
451d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
45272246da4SFelipe Balbi }
45372246da4SFelipe Balbi
45472246da4SFelipe Balbi /**
4551d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
45672246da4SFelipe Balbi * @dwc: Pointer to our controller context structure
45772246da4SFelipe Balbi * @length: size of the event buffer
45872246da4SFelipe Balbi *
4591d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success
46072246da4SFelipe Balbi * otherwise ERR_PTR(errno).
46172246da4SFelipe Balbi */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned int length)46267d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
463ca80ca61SKushagra Verma unsigned int length)
46472246da4SFelipe Balbi {
46572246da4SFelipe Balbi struct dwc3_event_buffer *evt;
46672246da4SFelipe Balbi
467380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
46872246da4SFelipe Balbi if (!evt)
46972246da4SFelipe Balbi return ERR_PTR(-ENOMEM);
47072246da4SFelipe Balbi
47172246da4SFelipe Balbi evt->dwc = dwc;
47272246da4SFelipe Balbi evt->length = length;
473d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
474d9fa4c63SJohn Youn if (!evt->cache)
475d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM);
476d9fa4c63SJohn Youn
477d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length,
47872246da4SFelipe Balbi &evt->dma, GFP_KERNEL);
479e32672f0SFelipe Balbi if (!evt->buf)
48072246da4SFelipe Balbi return ERR_PTR(-ENOMEM);
48172246da4SFelipe Balbi
48272246da4SFelipe Balbi return evt;
48372246da4SFelipe Balbi }
48472246da4SFelipe Balbi
48572246da4SFelipe Balbi /**
48672246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers
48772246da4SFelipe Balbi * @dwc: Pointer to our controller context structure
48872246da4SFelipe Balbi */
dwc3_free_event_buffers(struct dwc3 * dwc)48972246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc)
49072246da4SFelipe Balbi {
49172246da4SFelipe Balbi struct dwc3_event_buffer *evt;
49272246da4SFelipe Balbi
493696c8b12SFelipe Balbi evt = dwc->ev_buf;
49464b6c8a7SAnton Tikhomirov if (evt)
49572246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt);
49672246da4SFelipe Balbi }
49772246da4SFelipe Balbi
49872246da4SFelipe Balbi /**
49972246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
5001d046793SPaul Zimmerman * @dwc: pointer to our controller context structure
50172246da4SFelipe Balbi * @length: size of event buffer
50272246da4SFelipe Balbi *
5031d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc
50472246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested.
50572246da4SFelipe Balbi */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned int length)506ca80ca61SKushagra Verma static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
50772246da4SFelipe Balbi {
50872246da4SFelipe Balbi struct dwc3_event_buffer *evt;
50972246da4SFelipe Balbi
51072246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length);
51172246da4SFelipe Balbi if (IS_ERR(evt)) {
51272246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n");
51372246da4SFelipe Balbi return PTR_ERR(evt);
51472246da4SFelipe Balbi }
515696c8b12SFelipe Balbi dwc->ev_buf = evt;
51672246da4SFelipe Balbi
51772246da4SFelipe Balbi return 0;
51872246da4SFelipe Balbi }
51972246da4SFelipe Balbi
52072246da4SFelipe Balbi /**
52172246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers
5221d046793SPaul Zimmerman * @dwc: pointer to our controller context structure
52372246da4SFelipe Balbi *
52472246da4SFelipe Balbi * Returns 0 on success otherwise negative errno.
52572246da4SFelipe Balbi */
dwc3_event_buffers_setup(struct dwc3 * dwc)526f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc)
52772246da4SFelipe Balbi {
52872246da4SFelipe Balbi struct dwc3_event_buffer *evt;
52972246da4SFelipe Balbi
530696c8b12SFelipe Balbi evt = dwc->ev_buf;
5317acd85e0SPaul Zimmerman evt->lpos = 0;
532660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
53372246da4SFelipe Balbi lower_32_bits(evt->dma));
534660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
53572246da4SFelipe Balbi upper_32_bits(evt->dma));
536660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
53768d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length));
538660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
53972246da4SFelipe Balbi
54072246da4SFelipe Balbi return 0;
54172246da4SFelipe Balbi }
54272246da4SFelipe Balbi
dwc3_event_buffers_cleanup(struct dwc3 * dwc)543f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
54472246da4SFelipe Balbi {
54572246da4SFelipe Balbi struct dwc3_event_buffer *evt;
54672246da4SFelipe Balbi
547696c8b12SFelipe Balbi evt = dwc->ev_buf;
5487acd85e0SPaul Zimmerman
5497acd85e0SPaul Zimmerman evt->lpos = 0;
5507acd85e0SPaul Zimmerman
551660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
552660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
553660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
55468d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0));
555660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
55672246da4SFelipe Balbi }
55772246da4SFelipe Balbi
dwc3_core_num_eps(struct dwc3 * dwc)558789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc)
559789451f6SFelipe Balbi {
560789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams;
561789451f6SFelipe Balbi
56247d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms);
563789451f6SFelipe Balbi }
564789451f6SFelipe Balbi
dwc3_cache_hwparams(struct dwc3 * dwc)56541ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc)
56626ceca97SFelipe Balbi {
56726ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams;
56826ceca97SFelipe Balbi
56926ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
57026ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
57126ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
57226ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
57326ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
57426ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
57526ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
57626ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
57726ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
57816710380SThinh Nguyen
57916710380SThinh Nguyen if (DWC3_IP_IS(DWC32))
58016710380SThinh Nguyen parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
58126ceca97SFelipe Balbi }
58226ceca97SFelipe Balbi
dwc3_core_ulpi_init(struct dwc3 * dwc)58398112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc)
58498112041SRoger Quadros {
58598112041SRoger Quadros int intf;
58698112041SRoger Quadros int ret = 0;
58798112041SRoger Quadros
58898112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
58998112041SRoger Quadros
59098112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
59198112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
59298112041SRoger Quadros dwc->hsphy_interface &&
59398112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4)))
59498112041SRoger Quadros ret = dwc3_ulpi_init(dwc);
59598112041SRoger Quadros
59698112041SRoger Quadros return ret;
59798112041SRoger Quadros }
59898112041SRoger Quadros
59972246da4SFelipe Balbi /**
600b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
601b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure
60288bc9d19SHeikki Krogerus *
60388bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not
60488bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with
60588bc9d19SHeikki Krogerus * the core in dwc3_core_init.
606b5a65c40SHuang Rui */
dwc3_phy_setup(struct dwc3 * dwc)60788bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc)
608b5a65c40SHuang Rui {
609b5a65c40SHuang Rui u32 reg;
610b5a65c40SHuang Rui
611b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
612b5a65c40SHuang Rui
6132164a476SHuang Rui /*
6141966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some
6151966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation.
6161966b865SFelipe Balbi */
6171966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
6181966b865SFelipe Balbi
6191966b865SFelipe Balbi /*
620000f9944SThinh Nguyen * Above DWC_usb3.0 1.94a, it is recommended to set
621000f9944SThinh Nguyen * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration.
622000f9944SThinh Nguyen * So default value will be '0' when the core is reset. Application
623000f9944SThinh Nguyen * needs to set it to '1' after the core initialization is completed.
624000f9944SThinh Nguyen *
625000f9944SThinh Nguyen * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be
626000f9944SThinh Nguyen * cleared after power-on reset, and it can be set after core
627000f9944SThinh Nguyen * initialization.
6282164a476SHuang Rui */
6299ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
6309ba3aca8SThinh Nguyen
631b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk)
632b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
633b5a65c40SHuang Rui
634e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk)
635e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
636e58dd357SRajesh Bhagat
637df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk)
638df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
639df31f5b3SHuang Rui
640a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk)
641a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
642a2a1d0f5SHuang Rui
64341c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk)
64441c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
64541c06ffdSHuang Rui
646fb67afcaSHuang Rui if (dwc->lfps_filter_quirk)
647fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
648fb67afcaSHuang Rui
64914f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk)
65014f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
65114f4ac53SHuang Rui
6526b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk)
6536b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
6546b6a0c9aSHuang Rui
65500fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk)
65600fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
65700fe081dSWilliam Wu
658b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
659b5a65c40SHuang Rui
6602164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
6612164a476SHuang Rui
6623e10a2ceSHeikki Krogerus /* Select the HS PHY interface */
6633e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
6643e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
66543cacb03SFelipe Balbi if (dwc->hsphy_interface &&
66643cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) {
6673e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
66888bc9d19SHeikki Krogerus break;
66943cacb03SFelipe Balbi } else if (dwc->hsphy_interface &&
67043cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
6713e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
67288bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
6733e10a2ceSHeikki Krogerus } else {
67488bc9d19SHeikki Krogerus /* Relying on default value. */
67588bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
6763e10a2ceSHeikki Krogerus break;
6773e10a2ceSHeikki Krogerus }
678df561f66SGustavo A. R. Silva fallthrough;
67988bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
6803e10a2ceSHeikki Krogerus default:
6813e10a2ceSHeikki Krogerus break;
6823e10a2ceSHeikki Krogerus }
6833e10a2ceSHeikki Krogerus
68432f2ed86SWilliam Wu switch (dwc->hsphy_mode) {
68532f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI:
68632f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
68732f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
68832f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
68932f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
69032f2ed86SWilliam Wu break;
69132f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW:
69232f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
69332f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
69432f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
69532f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
69632f2ed86SWilliam Wu break;
69732f2ed86SWilliam Wu default:
69832f2ed86SWilliam Wu break;
69932f2ed86SWilliam Wu }
70032f2ed86SWilliam Wu
7012164a476SHuang Rui /*
702000f9944SThinh Nguyen * Above DWC_usb3.0 1.94a, it is recommended to set
703000f9944SThinh Nguyen * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration.
704000f9944SThinh Nguyen * So default value will be '0' when the core is reset. Application
705000f9944SThinh Nguyen * needs to set it to '1' after the core initialization is completed.
706000f9944SThinh Nguyen *
707000f9944SThinh Nguyen * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared
708000f9944SThinh Nguyen * after power-on reset, and it can be set after core initialization.
7092164a476SHuang Rui */
7100effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
7110effe0a3SHuang Rui
712ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk)
713ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
714eafeacf1SThinh Nguyen else
715eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
716ec791d14SJohn Youn
717a6fc2f1bSAlexander Stein if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
71816199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
71916199f33SWilliam Wu
720b84ba26cSPiyush Mehta /*
721b84ba26cSPiyush Mehta * Some ULPI USB PHY does not support internal VBUS supply, to drive
722b84ba26cSPiyush Mehta * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
723b84ba26cSPiyush Mehta * bit of OTG_CTRL register. Controller configures the USB2 PHY
724b84ba26cSPiyush Mehta * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
725b84ba26cSPiyush Mehta * with an external supply.
726b84ba26cSPiyush Mehta */
727b84ba26cSPiyush Mehta if (dwc->ulpi_ext_vbus_drv)
728b84ba26cSPiyush Mehta reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
729b84ba26cSPiyush Mehta
7302164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
73188bc9d19SHeikki Krogerus
73288bc9d19SHeikki Krogerus return 0;
733b5a65c40SHuang Rui }
734b5a65c40SHuang Rui
dwc3_phy_init(struct dwc3 * dwc)7351d72fab4SJohan Hovold static int dwc3_phy_init(struct dwc3 *dwc)
7361d72fab4SJohan Hovold {
7371d72fab4SJohan Hovold int ret;
7381d72fab4SJohan Hovold
7391d72fab4SJohan Hovold usb_phy_init(dwc->usb2_phy);
7401d72fab4SJohan Hovold usb_phy_init(dwc->usb3_phy);
7411d72fab4SJohan Hovold
7421d72fab4SJohan Hovold ret = phy_init(dwc->usb2_generic_phy);
7431d72fab4SJohan Hovold if (ret < 0)
7441d72fab4SJohan Hovold goto err_shutdown_usb3_phy;
7451d72fab4SJohan Hovold
7461d72fab4SJohan Hovold ret = phy_init(dwc->usb3_generic_phy);
7471d72fab4SJohan Hovold if (ret < 0)
7481d72fab4SJohan Hovold goto err_exit_usb2_phy;
7491d72fab4SJohan Hovold
7501d72fab4SJohan Hovold return 0;
7511d72fab4SJohan Hovold
7521d72fab4SJohan Hovold err_exit_usb2_phy:
7531d72fab4SJohan Hovold phy_exit(dwc->usb2_generic_phy);
7541d72fab4SJohan Hovold err_shutdown_usb3_phy:
7551d72fab4SJohan Hovold usb_phy_shutdown(dwc->usb3_phy);
7561d72fab4SJohan Hovold usb_phy_shutdown(dwc->usb2_phy);
7571d72fab4SJohan Hovold
7581d72fab4SJohan Hovold return ret;
7591d72fab4SJohan Hovold }
7601d72fab4SJohan Hovold
dwc3_phy_exit(struct dwc3 * dwc)7611d72fab4SJohan Hovold static void dwc3_phy_exit(struct dwc3 *dwc)
7621d72fab4SJohan Hovold {
7631d72fab4SJohan Hovold phy_exit(dwc->usb3_generic_phy);
7641d72fab4SJohan Hovold phy_exit(dwc->usb2_generic_phy);
7651d72fab4SJohan Hovold
7661d72fab4SJohan Hovold usb_phy_shutdown(dwc->usb3_phy);
7671d72fab4SJohan Hovold usb_phy_shutdown(dwc->usb2_phy);
7681d72fab4SJohan Hovold }
7691d72fab4SJohan Hovold
dwc3_phy_power_on(struct dwc3 * dwc)7701d72fab4SJohan Hovold static int dwc3_phy_power_on(struct dwc3 *dwc)
7711d72fab4SJohan Hovold {
7721d72fab4SJohan Hovold int ret;
7731d72fab4SJohan Hovold
7741d72fab4SJohan Hovold usb_phy_set_suspend(dwc->usb2_phy, 0);
7751d72fab4SJohan Hovold usb_phy_set_suspend(dwc->usb3_phy, 0);
7761d72fab4SJohan Hovold
7771d72fab4SJohan Hovold ret = phy_power_on(dwc->usb2_generic_phy);
7781d72fab4SJohan Hovold if (ret < 0)
7791d72fab4SJohan Hovold goto err_suspend_usb3_phy;
7801d72fab4SJohan Hovold
7811d72fab4SJohan Hovold ret = phy_power_on(dwc->usb3_generic_phy);
7821d72fab4SJohan Hovold if (ret < 0)
7831d72fab4SJohan Hovold goto err_power_off_usb2_phy;
7841d72fab4SJohan Hovold
7851d72fab4SJohan Hovold return 0;
7861d72fab4SJohan Hovold
7871d72fab4SJohan Hovold err_power_off_usb2_phy:
7881d72fab4SJohan Hovold phy_power_off(dwc->usb2_generic_phy);
7891d72fab4SJohan Hovold err_suspend_usb3_phy:
7901d72fab4SJohan Hovold usb_phy_set_suspend(dwc->usb3_phy, 1);
7911d72fab4SJohan Hovold usb_phy_set_suspend(dwc->usb2_phy, 1);
7921d72fab4SJohan Hovold
7931d72fab4SJohan Hovold return ret;
7941d72fab4SJohan Hovold }
7951d72fab4SJohan Hovold
dwc3_phy_power_off(struct dwc3 * dwc)7961d72fab4SJohan Hovold static void dwc3_phy_power_off(struct dwc3 *dwc)
7971d72fab4SJohan Hovold {
7981d72fab4SJohan Hovold phy_power_off(dwc->usb3_generic_phy);
7991d72fab4SJohan Hovold phy_power_off(dwc->usb2_generic_phy);
8001d72fab4SJohan Hovold
8011d72fab4SJohan Hovold usb_phy_set_suspend(dwc->usb3_phy, 1);
8021d72fab4SJohan Hovold usb_phy_set_suspend(dwc->usb2_phy, 1);
8031d72fab4SJohan Hovold }
8041d72fab4SJohan Hovold
dwc3_clk_enable(struct dwc3 * dwc)80533fb697eSSean Anderson static int dwc3_clk_enable(struct dwc3 *dwc)
80633fb697eSSean Anderson {
80733fb697eSSean Anderson int ret;
80833fb697eSSean Anderson
80933fb697eSSean Anderson ret = clk_prepare_enable(dwc->bus_clk);
81033fb697eSSean Anderson if (ret)
81133fb697eSSean Anderson return ret;
81233fb697eSSean Anderson
81333fb697eSSean Anderson ret = clk_prepare_enable(dwc->ref_clk);
81433fb697eSSean Anderson if (ret)
81533fb697eSSean Anderson goto disable_bus_clk;
81633fb697eSSean Anderson
81733fb697eSSean Anderson ret = clk_prepare_enable(dwc->susp_clk);
81833fb697eSSean Anderson if (ret)
81933fb697eSSean Anderson goto disable_ref_clk;
82033fb697eSSean Anderson
82133fb697eSSean Anderson return 0;
82233fb697eSSean Anderson
82333fb697eSSean Anderson disable_ref_clk:
82433fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk);
82533fb697eSSean Anderson disable_bus_clk:
82633fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk);
82733fb697eSSean Anderson return ret;
82833fb697eSSean Anderson }
82933fb697eSSean Anderson
dwc3_clk_disable(struct dwc3 * dwc)83033fb697eSSean Anderson static void dwc3_clk_disable(struct dwc3 *dwc)
83133fb697eSSean Anderson {
83233fb697eSSean Anderson clk_disable_unprepare(dwc->susp_clk);
83333fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk);
83433fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk);
83533fb697eSSean Anderson }
83633fb697eSSean Anderson
dwc3_core_exit(struct dwc3 * dwc)837c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc)
838c499ff71SFelipe Balbi {
839c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc);
8401d72fab4SJohan Hovold dwc3_phy_power_off(dwc);
8411d72fab4SJohan Hovold dwc3_phy_exit(dwc);
84233fb697eSSean Anderson dwc3_clk_disable(dwc);
843fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset);
844c499ff71SFelipe Balbi }
845c499ff71SFelipe Balbi
dwc3_core_is_valid(struct dwc3 * dwc)8460759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc)
84772246da4SFelipe Balbi {
84872246da4SFelipe Balbi u32 reg;
84972246da4SFelipe Balbi
8507650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
8519af21dd6SThinh Nguyen dwc->ip = DWC3_GSNPS_ID(reg);
8520759956fSFelipe Balbi
8537650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */
8549af21dd6SThinh Nguyen if (DWC3_IP_IS(DWC3)) {
855690fb371SJohn Youn dwc->revision = reg;
8569af21dd6SThinh Nguyen } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
857690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
858475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
859690fb371SJohn Youn } else {
8600759956fSFelipe Balbi return false;
8617650bd74SSebastian Andrzej Siewior }
8627650bd74SSebastian Andrzej Siewior
8630759956fSFelipe Balbi return true;
8640e1e5c47SPaul Zimmerman }
8650e1e5c47SPaul Zimmerman
dwc3_core_setup_global_control(struct dwc3 * dwc)866941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc)
86772246da4SFelipe Balbi {
86872246da4SFelipe Balbi u32 reg;
869c499ff71SFelipe Balbi
8704878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL);
8713e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
8724878a028SSebastian Andrzej Siewior
873164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
8744878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
87532a4a135SFelipe Balbi /**
87632a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
87732a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail.
87832a4a135SFelipe Balbi *
87932a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such
88032a4a135SFelipe Balbi * configurations.
88132a4a135SFelipe Balbi *
88232a4a135SFelipe Balbi * Refers to:
88332a4a135SFelipe Balbi *
88432a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
88532a4a135SFelipe Balbi * SOF/ITP Mode Used
88632a4a135SFelipe Balbi */
88732a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST ||
88832a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) &&
8899af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
89032a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
89132a4a135SFelipe Balbi else
8924878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG;
8934878a028SSebastian Andrzej Siewior break;
8940ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
8952eac3992SHuang Rui /*
8962eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation
8972eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented.
8982eac3992SHuang Rui */
8992eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN;
9000ffcaf37SFelipe Balbi break;
9014878a028SSebastian Andrzej Siewior default:
9025eb30cedSFelipe Balbi /* nothing */
9035eb30cedSFelipe Balbi break;
9044878a028SSebastian Andrzej Siewior }
9054878a028SSebastian Andrzej Siewior
906946bd579SHuang Rui /* check if current dwc3 is on simulation board */
907946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
9086af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n");
909946bd579SHuang Rui dwc->is_fpga = true;
910946bd579SHuang Rui }
911946bd579SHuang Rui
9123b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
9133b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n");
9143b81221aSHuang Rui
9153b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga)
9163b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE;
9173b81221aSHuang Rui else
9183b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE;
9193b81221aSHuang Rui
9209a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk)
9219a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS;
9229a5b2f31SHuang Rui
9234878a028SSebastian Andrzej Siewior /*
9244878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug
9251d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed
9264878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes
9271d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop
9284878a028SSebastian Andrzej Siewior */
9299af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 190A))
9304878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN;
9314878a028SSebastian Andrzej Siewior
9324878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg);
933941f918eSFelipe Balbi }
9344878a028SSebastian Andrzej Siewior
935f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc);
93698112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc);
937f54edb53SFelipe Balbi
938d9612c2fSPengbo Mu /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)939d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
940d9612c2fSPengbo Mu {
941d9612c2fSPengbo Mu struct device *dev = dwc->dev;
942d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */
943d9612c2fSPengbo Mu bool incrx_mode;
944d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */
945d9612c2fSPengbo Mu u32 incrx_size;
946d9612c2fSPengbo Mu u32 *vals;
947d9612c2fSPengbo Mu u32 cfg;
948d9612c2fSPengbo Mu int ntype;
949d9612c2fSPengbo Mu int ret;
950d9612c2fSPengbo Mu int i;
951d9612c2fSPengbo Mu
952d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
953d9612c2fSPengbo Mu
954d9612c2fSPengbo Mu /*
955d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment".
956d9612c2fSPengbo Mu * Get the number of value from this property:
957d9612c2fSPengbo Mu * result <= 0, means this property is not supported.
958d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported.
959d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported.
960d9612c2fSPengbo Mu */
961a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
962d9612c2fSPengbo Mu if (ntype <= 0)
963d9612c2fSPengbo Mu return;
964d9612c2fSPengbo Mu
965d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
9664ea15088SKushagra Verma if (!vals)
967d9612c2fSPengbo Mu return;
968d9612c2fSPengbo Mu
969d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */
970d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev,
971d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype);
972d9612c2fSPengbo Mu if (ret) {
97375ecb9ddSAndy Shevchenko kfree(vals);
974d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n");
975d9612c2fSPengbo Mu return;
976d9612c2fSPengbo Mu }
977d9612c2fSPengbo Mu
978d9612c2fSPengbo Mu incrx_size = *vals;
979d9612c2fSPengbo Mu
980d9612c2fSPengbo Mu if (ntype > 1) {
981d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */
982d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
983d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) {
984d9612c2fSPengbo Mu if (vals[i] > incrx_size)
985d9612c2fSPengbo Mu incrx_size = vals[i];
986d9612c2fSPengbo Mu }
987d9612c2fSPengbo Mu } else {
988d9612c2fSPengbo Mu /* INCRX burst mode */
989d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE;
990d9612c2fSPengbo Mu }
991d9612c2fSPengbo Mu
99275ecb9ddSAndy Shevchenko kfree(vals);
99375ecb9ddSAndy Shevchenko
994d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
995d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
996d9612c2fSPengbo Mu if (incrx_mode)
997d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
998d9612c2fSPengbo Mu switch (incrx_size) {
999d9612c2fSPengbo Mu case 256:
1000d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1001d9612c2fSPengbo Mu break;
1002d9612c2fSPengbo Mu case 128:
1003d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1004d9612c2fSPengbo Mu break;
1005d9612c2fSPengbo Mu case 64:
1006d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1007d9612c2fSPengbo Mu break;
1008d9612c2fSPengbo Mu case 32:
1009d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1010d9612c2fSPengbo Mu break;
1011d9612c2fSPengbo Mu case 16:
1012d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1013d9612c2fSPengbo Mu break;
1014d9612c2fSPengbo Mu case 8:
1015d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1016d9612c2fSPengbo Mu break;
1017d9612c2fSPengbo Mu case 4:
1018d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1019d9612c2fSPengbo Mu break;
1020d9612c2fSPengbo Mu case 1:
1021d9612c2fSPengbo Mu break;
1022d9612c2fSPengbo Mu default:
1023d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n");
1024d9612c2fSPengbo Mu break;
1025d9612c2fSPengbo Mu }
1026d9612c2fSPengbo Mu
1027d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1028d9612c2fSPengbo Mu }
1029d9612c2fSPengbo Mu
dwc3_set_power_down_clk_scale(struct dwc3 * dwc)10303497b9a5SLi Jun static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
10313497b9a5SLi Jun {
10323497b9a5SLi Jun u32 scale;
10333497b9a5SLi Jun u32 reg;
10343497b9a5SLi Jun
10353497b9a5SLi Jun if (!dwc->susp_clk)
10363497b9a5SLi Jun return;
10373497b9a5SLi Jun
10383497b9a5SLi Jun /*
10393497b9a5SLi Jun * The power down scale field specifies how many suspend_clk
10403497b9a5SLi Jun * periods fit into a 16KHz clock period. When performing
10413497b9a5SLi Jun * the division, round up the remainder.
10423497b9a5SLi Jun *
10433497b9a5SLi Jun * The power down scale value is calculated using the fastest
10443497b9a5SLi Jun * frequency of the suspend_clk. If it isn't fixed (but within
10453497b9a5SLi Jun * the accuracy requirement), the driver may not know the max
10463497b9a5SLi Jun * rate of the suspend_clk, so only update the power down scale
10473497b9a5SLi Jun * if the default is less than the calculated value from
10483497b9a5SLi Jun * clk_get_rate() or if the default is questionably high
10493497b9a5SLi Jun * (3x or more) to be within the requirement.
10503497b9a5SLi Jun */
10513497b9a5SLi Jun scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
10523497b9a5SLi Jun reg = dwc3_readl(dwc->regs, DWC3_GCTL);
10533497b9a5SLi Jun if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
10543497b9a5SLi Jun (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
10553497b9a5SLi Jun reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
10563497b9a5SLi Jun reg |= DWC3_GCTL_PWRDNSCALE(scale);
10573497b9a5SLi Jun dwc3_writel(dwc->regs, DWC3_GCTL, reg);
10583497b9a5SLi Jun }
10593497b9a5SLi Jun }
10603497b9a5SLi Jun
dwc3_config_threshold(struct dwc3 * dwc)1061a9876332SStanley Chang static void dwc3_config_threshold(struct dwc3 *dwc)
1062a9876332SStanley Chang {
1063a9876332SStanley Chang u32 reg;
1064a9876332SStanley Chang u8 rx_thr_num;
1065a9876332SStanley Chang u8 rx_maxburst;
1066a9876332SStanley Chang u8 tx_thr_num;
1067a9876332SStanley Chang u8 tx_maxburst;
1068a9876332SStanley Chang
1069a9876332SStanley Chang /*
1070a9876332SStanley Chang * Must config both number of packets and max burst settings to enable
1071a9876332SStanley Chang * RX and/or TX threshold.
1072a9876332SStanley Chang */
1073a9876332SStanley Chang if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1074a9876332SStanley Chang rx_thr_num = dwc->rx_thr_num_pkt_prd;
1075a9876332SStanley Chang rx_maxburst = dwc->rx_max_burst_prd;
1076a9876332SStanley Chang tx_thr_num = dwc->tx_thr_num_pkt_prd;
1077a9876332SStanley Chang tx_maxburst = dwc->tx_max_burst_prd;
1078a9876332SStanley Chang
1079a9876332SStanley Chang if (rx_thr_num && rx_maxburst) {
1080a9876332SStanley Chang reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1081a9876332SStanley Chang reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1082a9876332SStanley Chang
1083a9876332SStanley Chang reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1084a9876332SStanley Chang reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1085a9876332SStanley Chang
1086a9876332SStanley Chang reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1087a9876332SStanley Chang reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1088a9876332SStanley Chang
1089a9876332SStanley Chang dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1090a9876332SStanley Chang }
1091a9876332SStanley Chang
1092a9876332SStanley Chang if (tx_thr_num && tx_maxburst) {
1093a9876332SStanley Chang reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1094a9876332SStanley Chang reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1095a9876332SStanley Chang
1096a9876332SStanley Chang reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1097a9876332SStanley Chang reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1098a9876332SStanley Chang
1099a9876332SStanley Chang reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1100a9876332SStanley Chang reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1101a9876332SStanley Chang
1102a9876332SStanley Chang dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1103a9876332SStanley Chang }
1104a9876332SStanley Chang }
1105a9876332SStanley Chang
1106a9876332SStanley Chang rx_thr_num = dwc->rx_thr_num_pkt;
1107a9876332SStanley Chang rx_maxburst = dwc->rx_max_burst;
1108a9876332SStanley Chang tx_thr_num = dwc->tx_thr_num_pkt;
1109a9876332SStanley Chang tx_maxburst = dwc->tx_max_burst;
1110a9876332SStanley Chang
1111a9876332SStanley Chang if (DWC3_IP_IS(DWC3)) {
1112a9876332SStanley Chang if (rx_thr_num && rx_maxburst) {
1113a9876332SStanley Chang reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1114a9876332SStanley Chang reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1115a9876332SStanley Chang
1116a9876332SStanley Chang reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1117a9876332SStanley Chang reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1118a9876332SStanley Chang
1119a9876332SStanley Chang reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1120a9876332SStanley Chang reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1121a9876332SStanley Chang
1122a9876332SStanley Chang dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1123a9876332SStanley Chang }
1124a9876332SStanley Chang
1125a9876332SStanley Chang if (tx_thr_num && tx_maxburst) {
1126a9876332SStanley Chang reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1127a9876332SStanley Chang reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1128a9876332SStanley Chang
1129a9876332SStanley Chang reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1130a9876332SStanley Chang reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1131a9876332SStanley Chang
1132a9876332SStanley Chang reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1133a9876332SStanley Chang reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1134a9876332SStanley Chang
1135a9876332SStanley Chang dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1136a9876332SStanley Chang }
1137a9876332SStanley Chang } else {
1138a9876332SStanley Chang if (rx_thr_num && rx_maxburst) {
1139a9876332SStanley Chang reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1140a9876332SStanley Chang reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1141a9876332SStanley Chang
1142a9876332SStanley Chang reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1143a9876332SStanley Chang reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1144a9876332SStanley Chang
1145a9876332SStanley Chang reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1146a9876332SStanley Chang reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1147a9876332SStanley Chang
1148a9876332SStanley Chang dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1149a9876332SStanley Chang }
1150a9876332SStanley Chang
1151a9876332SStanley Chang if (tx_thr_num && tx_maxburst) {
1152a9876332SStanley Chang reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1153a9876332SStanley Chang reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1154a9876332SStanley Chang
1155a9876332SStanley Chang reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1156a9876332SStanley Chang reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1157a9876332SStanley Chang
1158a9876332SStanley Chang reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1159a9876332SStanley Chang reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1160a9876332SStanley Chang
1161a9876332SStanley Chang dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1162a9876332SStanley Chang }
1163a9876332SStanley Chang }
1164a9876332SStanley Chang }
1165a9876332SStanley Chang
1166941f918eSFelipe Balbi /**
1167941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core
1168941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure
1169941f918eSFelipe Balbi *
1170941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno.
1171941f918eSFelipe Balbi */
dwc3_core_init(struct dwc3 * dwc)1172941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc)
1173941f918eSFelipe Balbi {
11749ba3aca8SThinh Nguyen unsigned int hw_mode;
1175941f918eSFelipe Balbi u32 reg;
1176941f918eSFelipe Balbi int ret;
1177941f918eSFelipe Balbi
11789ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
11799ba3aca8SThinh Nguyen
1180941f918eSFelipe Balbi /*
1181941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure
1182941f918eSFelipe Balbi * out which kernel version a bug was found.
1183941f918eSFelipe Balbi */
1184941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1185941f918eSFelipe Balbi
1186941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc);
1187941f918eSFelipe Balbi if (ret)
1188d2f19782SJohan Hovold return ret;
1189941f918eSFelipe Balbi
119098112041SRoger Quadros if (!dwc->ulpi_ready) {
119198112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc);
119263130462SFerry Toth if (ret) {
119363130462SFerry Toth if (ret == -ETIMEDOUT) {
119463130462SFerry Toth dwc3_core_soft_reset(dwc);
119563130462SFerry Toth ret = -EPROBE_DEFER;
119663130462SFerry Toth }
1197d2f19782SJohan Hovold return ret;
119863130462SFerry Toth }
119998112041SRoger Quadros dwc->ulpi_ready = true;
120098112041SRoger Quadros }
120198112041SRoger Quadros
120298112041SRoger Quadros if (!dwc->phys_ready) {
120398112041SRoger Quadros ret = dwc3_core_get_phy(dwc);
120498112041SRoger Quadros if (ret)
1205d2f19782SJohan Hovold goto err_exit_ulpi;
120698112041SRoger Quadros dwc->phys_ready = true;
120798112041SRoger Quadros }
120898112041SRoger Quadros
12091d72fab4SJohan Hovold ret = dwc3_phy_init(dwc);
12101d72fab4SJohan Hovold if (ret)
12111d72fab4SJohan Hovold goto err_exit_ulpi;
12128cfac9a6SLi Jun
121398112041SRoger Quadros ret = dwc3_core_soft_reset(dwc);
121498112041SRoger Quadros if (ret)
12151d72fab4SJohan Hovold goto err_exit_phy;
121698112041SRoger Quadros
1217941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc);
1218c499ff71SFelipe Balbi dwc3_core_num_eps(dwc);
12190ffcaf37SFelipe Balbi
12203497b9a5SLi Jun /* Set power down scale of suspend_clk */
12213497b9a5SLi Jun dwc3_set_power_down_clk_scale(dwc);
12223497b9a5SLi Jun
1223c499ff71SFelipe Balbi /* Adjust Frame Length */
1224c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc);
1225c499ff71SFelipe Balbi
12267bee3188SBalaji Prakash J /* Adjust Reference Clock Period */
12277bee3188SBalaji Prakash J dwc3_ref_clk_period(dwc);
12287bee3188SBalaji Prakash J
1229d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc);
1230d9612c2fSPengbo Mu
12318018018dSDan Carpenter ret = dwc3_phy_power_on(dwc);
12321d72fab4SJohan Hovold if (ret)
12331d72fab4SJohan Hovold goto err_exit_phy;
1234c499ff71SFelipe Balbi
1235c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc);
1236c499ff71SFelipe Balbi if (ret) {
1237c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n");
12381d72fab4SJohan Hovold goto err_power_off_phy;
1239c499ff71SFelipe Balbi }
1240c499ff71SFelipe Balbi
124106281d46SJohn Youn /*
124206281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of
124306281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the
124406281d46SJohn Youn * DWC_usb31 controller.
124506281d46SJohn Youn */
12469af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
124706281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
124806281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER;
124906281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
125006281d46SJohn Youn }
125106281d46SJohn Youn
125263d7f981SPiyush Mehta /*
125363d7f981SPiyush Mehta * When configured in HOST mode, after issuing U3/L2 exit controller
125463d7f981SPiyush Mehta * fails to send proper CRC checksum in CRC5 feild. Because of this
125563d7f981SPiyush Mehta * behaviour Transaction Error is generated, resulting in reset and
125663d7f981SPiyush Mehta * re-enumeration of usb device attached. All the termsel, xcvrsel,
125763d7f981SPiyush Mehta * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
125863d7f981SPiyush Mehta * will correct this problem. This option is to support certain
125963d7f981SPiyush Mehta * legacy ULPI PHYs.
126063d7f981SPiyush Mehta */
126163d7f981SPiyush Mehta if (dwc->resume_hs_terminations) {
126263d7f981SPiyush Mehta reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
126363d7f981SPiyush Mehta reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
126463d7f981SPiyush Mehta dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
126563d7f981SPiyush Mehta }
126663d7f981SPiyush Mehta
12679af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
12680bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
126965db7a0cSWilliam Wu
127065db7a0cSWilliam Wu /*
127165db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup
127265db7a0cSWilliam Wu * in HS when the device is in the L1 state.
127365db7a0cSWilliam Wu */
12749af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
12750bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
127665db7a0cSWilliam Wu
1277843714bbSJack Pham /*
1278843714bbSJack Pham * Decouple USB 2.0 L1 & L2 events which will allow for
1279843714bbSJack Pham * gadget driver to only receive U3/L2 suspend & wakeup
1280843714bbSJack Pham * events and prevent the more frequent L1 LPM transitions
1281843714bbSJack Pham * from interrupting the driver.
1282843714bbSJack Pham */
1283843714bbSJack Pham if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1284843714bbSJack Pham reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1285843714bbSJack Pham
128665db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk)
128765db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
128865db7a0cSWilliam Wu
12897ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk)
12907ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
12917ba6b09fSNeil Armstrong
1292d21a797aSStanley Chang if (dwc->parkmode_disable_hs_quirk)
1293d21a797aSStanley Chang reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1294d21a797aSStanley Chang
129562b20e6eSBin Yang if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
129662b20e6eSBin Yang (dwc->maximum_speed == USB_SPEED_HIGH ||
129762b20e6eSBin Yang dwc->maximum_speed == USB_SPEED_FULL))
129862b20e6eSBin Yang reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
129962b20e6eSBin Yang
13000bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
13010bb39ca1SJohn Youn }
13020bb39ca1SJohn Youn
1303a9876332SStanley Chang dwc3_config_threshold(dwc);
1304938a5ad1SThinh Nguyen
130572246da4SFelipe Balbi return 0;
130672246da4SFelipe Balbi
13071d72fab4SJohan Hovold err_power_off_phy:
13081d72fab4SJohan Hovold dwc3_phy_power_off(dwc);
13091d72fab4SJohan Hovold err_exit_phy:
13101d72fab4SJohan Hovold dwc3_phy_exit(dwc);
1311d2f19782SJohan Hovold err_exit_ulpi:
131298112041SRoger Quadros dwc3_ulpi_exit(dwc);
131398112041SRoger Quadros
131472246da4SFelipe Balbi return ret;
131572246da4SFelipe Balbi }
131672246da4SFelipe Balbi
dwc3_core_get_phy(struct dwc3 * dwc)13173c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc)
131872246da4SFelipe Balbi {
13193c9f94acSFelipe Balbi struct device *dev = dwc->dev;
1320941ea361SFelipe Balbi struct device_node *node = dev->of_node;
13213c9f94acSFelipe Balbi int ret;
132272246da4SFelipe Balbi
13235088b6f5SKishon Vijay Abraham I if (node) {
13245088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
13255088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1326bb674907SFelipe Balbi } else {
1327bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1328bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
13295088b6f5SKishon Vijay Abraham I }
13305088b6f5SKishon Vijay Abraham I
1331d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) {
1332d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy);
1333d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV)
1334122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL;
1335d090c7a2SKushagra Verma else
13360c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1337122f06e6SKishon Vijay Abraham I }
133851e1e7bcSFelipe Balbi
1339d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) {
1340315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy);
1341d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV)
1342122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL;
1343d090c7a2SKushagra Verma else
13440c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1345122f06e6SKishon Vijay Abraham I }
134651e1e7bcSFelipe Balbi
134757303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
134857303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) {
134957303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy);
1350fb119dcbSThinh Nguyen if (ret == -ENOSYS || ret == -ENODEV)
135157303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL;
1352d090c7a2SKushagra Verma else
13530c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n");
135457303488SKishon Vijay Abraham I }
135557303488SKishon Vijay Abraham I
135657303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
135757303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) {
135857303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy);
1359fb119dcbSThinh Nguyen if (ret == -ENOSYS || ret == -ENODEV)
136057303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL;
1361d090c7a2SKushagra Verma else
13620c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n");
136357303488SKishon Vijay Abraham I }
136457303488SKishon Vijay Abraham I
13653c9f94acSFelipe Balbi return 0;
13663c9f94acSFelipe Balbi }
13673c9f94acSFelipe Balbi
dwc3_core_init_mode(struct dwc3 * dwc)13685f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc)
13695f94adfeSFelipe Balbi {
13705f94adfeSFelipe Balbi struct device *dev = dwc->dev;
13715f94adfeSFelipe Balbi int ret;
13725f94adfeSFelipe Balbi
13735f94adfeSFelipe Balbi switch (dwc->dr_mode) {
13745f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL:
137541ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1376958d1a4cSFelipe Balbi
1377958d1a4cSFelipe Balbi if (dwc->usb2_phy)
1378958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false);
1379958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1380644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1381958d1a4cSFelipe Balbi
13825f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc);
13830c0a20f6SAndy Shevchenko if (ret)
13840c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize gadget\n");
13855f94adfeSFelipe Balbi break;
13865f94adfeSFelipe Balbi case USB_DR_MODE_HOST:
138741ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1388958d1a4cSFelipe Balbi
1389958d1a4cSFelipe Balbi if (dwc->usb2_phy)
1390958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true);
1391958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1392644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1393958d1a4cSFelipe Balbi
13945f94adfeSFelipe Balbi ret = dwc3_host_init(dwc);
13950c0a20f6SAndy Shevchenko if (ret)
13960c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize host\n");
13975f94adfeSFelipe Balbi break;
13985f94adfeSFelipe Balbi case USB_DR_MODE_OTG:
139941ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
14009840354fSRoger Quadros ret = dwc3_drd_init(dwc);
14010c0a20f6SAndy Shevchenko if (ret)
14020c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
14035f94adfeSFelipe Balbi break;
14045f94adfeSFelipe Balbi default:
14055f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
14065f94adfeSFelipe Balbi return -EINVAL;
14075f94adfeSFelipe Balbi }
14085f94adfeSFelipe Balbi
14095f94adfeSFelipe Balbi return 0;
14105f94adfeSFelipe Balbi }
14115f94adfeSFelipe Balbi
dwc3_core_exit_mode(struct dwc3 * dwc)14125f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc)
14135f94adfeSFelipe Balbi {
14145f94adfeSFelipe Balbi switch (dwc->dr_mode) {
14155f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL:
14165f94adfeSFelipe Balbi dwc3_gadget_exit(dwc);
14175f94adfeSFelipe Balbi break;
14185f94adfeSFelipe Balbi case USB_DR_MODE_HOST:
14195f94adfeSFelipe Balbi dwc3_host_exit(dwc);
14205f94adfeSFelipe Balbi break;
14215f94adfeSFelipe Balbi case USB_DR_MODE_OTG:
14229840354fSRoger Quadros dwc3_drd_exit(dwc);
14235f94adfeSFelipe Balbi break;
14245f94adfeSFelipe Balbi default:
14255f94adfeSFelipe Balbi /* do nothing */
14265f94adfeSFelipe Balbi break;
14275f94adfeSFelipe Balbi }
142809ed259fSBin Liu
142909ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */
143009ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
14315f94adfeSFelipe Balbi }
14325f94adfeSFelipe Balbi
dwc3_get_properties(struct dwc3 * dwc)1433c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc)
14343c9f94acSFelipe Balbi {
1435c5ac6116SFelipe Balbi struct device *dev = dwc->dev;
143680caf7d2SHuang Rui u8 lpm_nyet_threshold;
14376b6a0c9aSHuang Rui u8 tx_de_emphasis;
1438460d098cSHuang Rui u8 hird_threshold;
1439a9876332SStanley Chang u8 rx_thr_num_pkt = 0;
1440a9876332SStanley Chang u8 rx_max_burst = 0;
1441a9876332SStanley Chang u8 tx_thr_num_pkt = 0;
1442a9876332SStanley Chang u8 tx_max_burst = 0;
1443f28ad906SThinh Nguyen u8 rx_thr_num_pkt_prd = 0;
1444f28ad906SThinh Nguyen u8 rx_max_burst_prd = 0;
1445f28ad906SThinh Nguyen u8 tx_thr_num_pkt_prd = 0;
1446f28ad906SThinh Nguyen u8 tx_max_burst_prd = 0;
14479f607a30SWesley Cheng u8 tx_fifo_resize_max_num;
14486f0764b5SRay Chi const char *usb_psy_name;
14496f0764b5SRay Chi int ret;
14503c9f94acSFelipe Balbi
145180caf7d2SHuang Rui /* default to highest possible threshold */
14528d791929SThinh Nguyen lpm_nyet_threshold = 0xf;
145380caf7d2SHuang Rui
14546b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */
14556b6a0c9aSHuang Rui tx_de_emphasis = 1;
14566b6a0c9aSHuang Rui
1457460d098cSHuang Rui /*
1458460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD
1459460d098cSHuang Rui * threshold value of 0b1100
1460460d098cSHuang Rui */
1461460d098cSHuang Rui hird_threshold = 12;
1462460d098cSHuang Rui
14639f607a30SWesley Cheng /*
14649f607a30SWesley Cheng * default to a TXFIFO size large enough to fit 6 max packets. This
14659f607a30SWesley Cheng * allows for systems with larger bus latencies to have some headroom
14669f607a30SWesley Cheng * for endpoints that have a large bMaxBurst value.
14679f607a30SWesley Cheng */
14689f607a30SWesley Cheng tx_fifo_resize_max_num = 6;
14699f607a30SWesley Cheng
147063863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev);
147167848146SThinh Nguyen dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
147206e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev);
147332f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
147463863b98SHeikki Krogerus
1475d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev,
1476d64ff406SArnd Bergmann "linux,sysdev_is_parent");
1477d64ff406SArnd Bergmann if (dwc->sysdev_is_parent)
1478d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent;
1479d64ff406SArnd Bergmann else
1480d64ff406SArnd Bergmann dwc->sysdev = dwc->dev;
1481d64ff406SArnd Bergmann
1482fd2304f4SThinh Nguyen dwc->sys_wakeup = device_may_wakeup(dwc->sysdev);
1483fd2304f4SThinh Nguyen
14846f0764b5SRay Chi ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
14856f0764b5SRay Chi if (ret >= 0) {
14866f0764b5SRay Chi dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
14876f0764b5SRay Chi if (!dwc->usb_psy)
14886f0764b5SRay Chi dev_err(dev, "couldn't get usb power supply\n");
14896f0764b5SRay Chi }
14906f0764b5SRay Chi
14913d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev,
149280caf7d2SHuang Rui "snps,has-lpm-erratum");
14933d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold",
149480caf7d2SHuang Rui &lpm_nyet_threshold);
14953d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1496460d098cSHuang Rui "snps,is-utmi-l1-suspend");
14973d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold",
1498460d098cSHuang Rui &hird_threshold);
1499d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1500d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk");
15013d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev,
1502eac68e8fSRobert Baldyga "snps,usb3_lpm_capable");
1503022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev,
1504022a0208SThinh Nguyen "snps,usb2-lpm-disable");
1505475e8be5SThinh Nguyen dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1506475e8be5SThinh Nguyen "snps,usb2-gadget-lpm-disable");
1507a9876332SStanley Chang device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1508a9876332SStanley Chang &rx_thr_num_pkt);
1509a9876332SStanley Chang device_property_read_u8(dev, "snps,rx-max-burst",
1510a9876332SStanley Chang &rx_max_burst);
1511a9876332SStanley Chang device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1512a9876332SStanley Chang &tx_thr_num_pkt);
1513a9876332SStanley Chang device_property_read_u8(dev, "snps,tx-max-burst",
1514a9876332SStanley Chang &tx_max_burst);
1515938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1516938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd);
1517938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd",
1518938a5ad1SThinh Nguyen &rx_max_burst_prd);
1519938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1520938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd);
1521938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd",
1522938a5ad1SThinh Nguyen &tx_max_burst_prd);
15239f607a30SWesley Cheng dwc->do_fifo_resize = device_property_read_bool(dev,
15249f607a30SWesley Cheng "tx-fifo-resize");
15259f607a30SWesley Cheng if (dwc->do_fifo_resize)
15269f607a30SWesley Cheng device_property_read_u8(dev, "tx-fifo-max-num",
15279f607a30SWesley Cheng &tx_fifo_resize_max_num);
15283c9f94acSFelipe Balbi
15293d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev,
15303b81221aSHuang Rui "snps,disable_scramble_quirk");
15313d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
15329a5b2f31SHuang Rui "snps,u2exit_lfps_quirk");
15333d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1534b5a65c40SHuang Rui "snps,u2ss_inp3_quirk");
15353d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1536df31f5b3SHuang Rui "snps,req_p1p2p3_quirk");
15373d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1538a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk");
15393d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
154041c06ffdSHuang Rui "snps,del_phy_power_chg_quirk");
15413d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev,
1542fb67afcaSHuang Rui "snps,lfps_filter_quirk");
15433d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
154414f4ac53SHuang Rui "snps,rx_detect_poll_quirk");
15453d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
154659acfa20SHuang Rui "snps,dis_u3_susphy_quirk");
15473d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
15480effe0a3SHuang Rui "snps,dis_u2_susphy_quirk");
1549ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1550ec791d14SJohn Youn "snps,dis_enblslpm_quirk");
1551729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1552729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk");
1553729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1554729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk");
1555e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1556e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk");
155716199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
155816199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk");
155900fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
156000fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk");
156165db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
156265db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk");
156363d7f981SPiyush Mehta dwc->resume_hs_terminations = device_property_read_bool(dev,
156463d7f981SPiyush Mehta "snps,resume-hs-terminations");
1565b84ba26cSPiyush Mehta dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1566b84ba26cSPiyush Mehta "snps,ulpi-ext-vbus-drv");
15677ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
15687ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk");
1569d21a797aSStanley Chang dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1570d21a797aSStanley Chang "snps,parkmode-disable-hs-quirk");
1571a6fc2f1bSAlexander Stein dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1572a6fc2f1bSAlexander Stein "snps,gfladj-refclk-lpm-sel-quirk");
15736b6a0c9aSHuang Rui
15743d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
15756b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk");
15763d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis",
15776b6a0c9aSHuang Rui &tx_de_emphasis);
15783d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface",
15793e10a2ceSHeikki Krogerus &dwc->hsphy_interface);
15803d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1581bcdb3272SFelipe Balbi &dwc->fladj);
15827bee3188SBalaji Prakash J device_property_read_u32(dev, "snps,ref-clock-period-ns",
15837bee3188SBalaji Prakash J &dwc->ref_clk_per);
15843d128919SHeikki Krogerus
158542bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev,
158642bf02ecSRoger Quadros "snps,dis_metastability_quirk");
158742bf02ecSRoger Quadros
1588f580170fSYu Chen dwc->dis_split_quirk = device_property_read_bool(dev,
1589f580170fSYu Chen "snps,dis-split-quirk");
1590f580170fSYu Chen
159180caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold;
15926b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis;
159380caf7d2SHuang Rui
159416fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold;
1595460d098cSHuang Rui
1596a9876332SStanley Chang dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1597a9876332SStanley Chang dwc->rx_max_burst = rx_max_burst;
1598a9876332SStanley Chang
1599a9876332SStanley Chang dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1600a9876332SStanley Chang dwc->tx_max_burst = tx_max_burst;
1601a9876332SStanley Chang
1602938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1603938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd;
1604938a5ad1SThinh Nguyen
1605938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1606938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd;
1607938a5ad1SThinh Nguyen
1608cf40b86bSJohn Youn dwc->imod_interval = 0;
16099f607a30SWesley Cheng
16109f607a30SWesley Cheng dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1611cf40b86bSJohn Youn }
1612cf40b86bSJohn Youn
1613cf40b86bSJohn Youn /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1614cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc)
1615cf40b86bSJohn Youn {
16169af21dd6SThinh Nguyen return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
16179af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
16189af21dd6SThinh Nguyen DWC3_IP_IS(DWC32);
1619c5ac6116SFelipe Balbi }
1620c5ac6116SFelipe Balbi
dwc3_check_params(struct dwc3 * dwc)16217ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc)
16227ac51a12SJohn Youn {
16237ac51a12SJohn Youn struct device *dev = dwc->dev;
1624b574ce3eSThinh Nguyen unsigned int hwparam_gen =
1625b574ce3eSThinh Nguyen DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
16267ac51a12SJohn Youn
1627cf40b86bSJohn Youn /* Check for proper value of imod_interval */
1628cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1629cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1630cf40b86bSJohn Youn dwc->imod_interval = 0;
1631cf40b86bSJohn Youn }
1632cf40b86bSJohn Youn
163328632b44SJohn Youn /*
163428632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version
163528632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller
163628632b44SJohn Youn * interrupt from being masked while handling events. IMOD
163728632b44SJohn Youn * allows us to work around this issue. Enable it for the
163828632b44SJohn Youn * affected version.
163928632b44SJohn Youn */
164028632b44SJohn Youn if (!dwc->imod_interval &&
16419af21dd6SThinh Nguyen DWC3_VER_IS(DWC3, 300A))
164228632b44SJohn Youn dwc->imod_interval = 1;
164328632b44SJohn Youn
16447ac51a12SJohn Youn /* Check the maximum_speed parameter */
16457ac51a12SJohn Youn switch (dwc->maximum_speed) {
16467ac51a12SJohn Youn case USB_SPEED_FULL:
16477ac51a12SJohn Youn case USB_SPEED_HIGH:
1648e518bdd9SThinh Nguyen break;
16497ac51a12SJohn Youn case USB_SPEED_SUPER:
1650e518bdd9SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1651e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support Gen 1\n");
1652e518bdd9SThinh Nguyen break;
16537ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS:
1654e518bdd9SThinh Nguyen if ((DWC3_IP_IS(DWC32) &&
1655e518bdd9SThinh Nguyen hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1656e518bdd9SThinh Nguyen (!DWC3_IP_IS(DWC32) &&
1657e518bdd9SThinh Nguyen hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1658e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support SSP\n");
16597ac51a12SJohn Youn break;
16607ac51a12SJohn Youn default:
16617ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n",
16627ac51a12SJohn Youn dwc->maximum_speed);
1663df561f66SGustavo A. R. Silva fallthrough;
16647ac51a12SJohn Youn case USB_SPEED_UNKNOWN:
1665b574ce3eSThinh Nguyen switch (hwparam_gen) {
1666b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
16677ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1668b574ce3eSThinh Nguyen break;
1669b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1670b574ce3eSThinh Nguyen if (DWC3_IP_IS(DWC32))
1671b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1672b574ce3eSThinh Nguyen else
1673b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER;
1674b574ce3eSThinh Nguyen break;
1675b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1676b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_HIGH;
1677b574ce3eSThinh Nguyen break;
1678b574ce3eSThinh Nguyen default:
1679b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER;
1680b574ce3eSThinh Nguyen break;
1681b574ce3eSThinh Nguyen }
16827ac51a12SJohn Youn break;
16837ac51a12SJohn Youn }
168467848146SThinh Nguyen
168567848146SThinh Nguyen /*
168667848146SThinh Nguyen * Currently the controller does not have visibility into the HW
168767848146SThinh Nguyen * parameter to determine the maximum number of lanes the HW supports.
168867848146SThinh Nguyen * If the number of lanes is not specified in the device property, then
168967848146SThinh Nguyen * set the default to support dual-lane for DWC_usb32 and single-lane
169067848146SThinh Nguyen * for DWC_usb31 for super-speed-plus.
169167848146SThinh Nguyen */
169267848146SThinh Nguyen if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
169367848146SThinh Nguyen switch (dwc->max_ssp_rate) {
169467848146SThinh Nguyen case USB_SSP_GEN_2x1:
169567848146SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
169667848146SThinh Nguyen dev_warn(dev, "UDC only supports Gen 1\n");
169767848146SThinh Nguyen break;
169867848146SThinh Nguyen case USB_SSP_GEN_1x2:
169967848146SThinh Nguyen case USB_SSP_GEN_2x2:
170067848146SThinh Nguyen if (DWC3_IP_IS(DWC31))
170167848146SThinh Nguyen dev_warn(dev, "UDC only supports single lane\n");
170267848146SThinh Nguyen break;
170367848146SThinh Nguyen case USB_SSP_GEN_UNKNOWN:
170467848146SThinh Nguyen default:
170567848146SThinh Nguyen switch (hwparam_gen) {
170667848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
170767848146SThinh Nguyen if (DWC3_IP_IS(DWC32))
170867848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x2;
170967848146SThinh Nguyen else
171067848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x1;
171167848146SThinh Nguyen break;
171267848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
171367848146SThinh Nguyen if (DWC3_IP_IS(DWC32))
171467848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_1x2;
171567848146SThinh Nguyen break;
171667848146SThinh Nguyen }
171767848146SThinh Nguyen break;
171867848146SThinh Nguyen }
171967848146SThinh Nguyen }
17207ac51a12SJohn Youn }
17217ac51a12SJohn Youn
dwc3_get_extcon(struct dwc3 * dwc)1722d182c2e1SAndrey Smirnov static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1723d182c2e1SAndrey Smirnov {
1724d182c2e1SAndrey Smirnov struct device *dev = dwc->dev;
1725d182c2e1SAndrey Smirnov struct device_node *np_phy;
1726d182c2e1SAndrey Smirnov struct extcon_dev *edev = NULL;
1727d182c2e1SAndrey Smirnov const char *name;
1728d182c2e1SAndrey Smirnov
1729d182c2e1SAndrey Smirnov if (device_property_read_bool(dev, "extcon"))
1730d182c2e1SAndrey Smirnov return extcon_get_edev_by_phandle(dev, 0);
1731d182c2e1SAndrey Smirnov
1732d182c2e1SAndrey Smirnov /*
1733d182c2e1SAndrey Smirnov * Device tree platforms should get extcon via phandle.
1734d182c2e1SAndrey Smirnov * On ACPI platforms, we get the name from a device property.
1735d182c2e1SAndrey Smirnov * This device property is for kernel internal use only and
1736d182c2e1SAndrey Smirnov * is expected to be set by the glue code.
1737d182c2e1SAndrey Smirnov */
1738d182c2e1SAndrey Smirnov if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1739d182c2e1SAndrey Smirnov return extcon_get_extcon_dev(name);
1740d182c2e1SAndrey Smirnov
1741d182c2e1SAndrey Smirnov /*
1742d68cc25bSJanne Grunau * Check explicitly if "usb-role-switch" is used since
1743d68cc25bSJanne Grunau * extcon_find_edev_by_node() can not be used to check the absence of
1744d68cc25bSJanne Grunau * an extcon device. In the absence of an device it will always return
1745d68cc25bSJanne Grunau * EPROBE_DEFER.
1746d68cc25bSJanne Grunau */
1747d68cc25bSJanne Grunau if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1748d68cc25bSJanne Grunau device_property_read_bool(dev, "usb-role-switch"))
1749d68cc25bSJanne Grunau return NULL;
1750d68cc25bSJanne Grunau
1751d68cc25bSJanne Grunau /*
1752d182c2e1SAndrey Smirnov * Try to get an extcon device from the USB PHY controller's "port"
1753d182c2e1SAndrey Smirnov * node. Check if it has the "port" node first, to avoid printing the
1754d182c2e1SAndrey Smirnov * error message from underlying code, as it's a valid case: extcon
1755d182c2e1SAndrey Smirnov * device (and "port" node) may be missing in case of "usb-role-switch"
1756d182c2e1SAndrey Smirnov * or OTG mode.
1757d182c2e1SAndrey Smirnov */
1758d182c2e1SAndrey Smirnov np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1759d182c2e1SAndrey Smirnov if (of_graph_is_present(np_phy)) {
1760d182c2e1SAndrey Smirnov struct device_node *np_conn;
1761d182c2e1SAndrey Smirnov
1762d182c2e1SAndrey Smirnov np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1763d182c2e1SAndrey Smirnov if (np_conn)
1764d182c2e1SAndrey Smirnov edev = extcon_find_edev_by_node(np_conn);
1765d182c2e1SAndrey Smirnov of_node_put(np_conn);
1766d182c2e1SAndrey Smirnov }
1767d182c2e1SAndrey Smirnov of_node_put(np_phy);
1768d182c2e1SAndrey Smirnov
1769d182c2e1SAndrey Smirnov return edev;
1770d182c2e1SAndrey Smirnov }
1771d182c2e1SAndrey Smirnov
dwc3_get_clocks(struct dwc3 * dwc)1772bd828574SJohan Hovold static int dwc3_get_clocks(struct dwc3 *dwc)
1773bd828574SJohan Hovold {
1774bd828574SJohan Hovold struct device *dev = dwc->dev;
1775bd828574SJohan Hovold
1776bd828574SJohan Hovold if (!dev->of_node)
1777bd828574SJohan Hovold return 0;
1778bd828574SJohan Hovold
1779bd828574SJohan Hovold /*
1780bd828574SJohan Hovold * Clocks are optional, but new DT platforms should support all clocks
1781bd828574SJohan Hovold * as required by the DT-binding.
1782bd828574SJohan Hovold * Some devices have different clock names in legacy device trees,
1783bd828574SJohan Hovold * check for them to retain backwards compatibility.
1784bd828574SJohan Hovold */
1785bd828574SJohan Hovold dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1786bd828574SJohan Hovold if (IS_ERR(dwc->bus_clk)) {
1787bd828574SJohan Hovold return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1788bd828574SJohan Hovold "could not get bus clock\n");
1789bd828574SJohan Hovold }
1790bd828574SJohan Hovold
1791bd828574SJohan Hovold if (dwc->bus_clk == NULL) {
1792bd828574SJohan Hovold dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1793bd828574SJohan Hovold if (IS_ERR(dwc->bus_clk)) {
1794bd828574SJohan Hovold return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1795bd828574SJohan Hovold "could not get bus clock\n");
1796bd828574SJohan Hovold }
1797bd828574SJohan Hovold }
1798bd828574SJohan Hovold
1799bd828574SJohan Hovold dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1800bd828574SJohan Hovold if (IS_ERR(dwc->ref_clk)) {
1801bd828574SJohan Hovold return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1802bd828574SJohan Hovold "could not get ref clock\n");
1803bd828574SJohan Hovold }
1804bd828574SJohan Hovold
1805bd828574SJohan Hovold if (dwc->ref_clk == NULL) {
1806bd828574SJohan Hovold dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1807bd828574SJohan Hovold if (IS_ERR(dwc->ref_clk)) {
1808bd828574SJohan Hovold return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1809bd828574SJohan Hovold "could not get ref clock\n");
1810bd828574SJohan Hovold }
1811bd828574SJohan Hovold }
1812bd828574SJohan Hovold
1813bd828574SJohan Hovold dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1814bd828574SJohan Hovold if (IS_ERR(dwc->susp_clk)) {
1815bd828574SJohan Hovold return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1816bd828574SJohan Hovold "could not get suspend clock\n");
1817bd828574SJohan Hovold }
1818bd828574SJohan Hovold
1819bd828574SJohan Hovold if (dwc->susp_clk == NULL) {
1820bd828574SJohan Hovold dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1821bd828574SJohan Hovold if (IS_ERR(dwc->susp_clk)) {
1822bd828574SJohan Hovold return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1823bd828574SJohan Hovold "could not get suspend clock\n");
1824bd828574SJohan Hovold }
1825bd828574SJohan Hovold }
1826bd828574SJohan Hovold
1827bd828574SJohan Hovold return 0;
1828bd828574SJohan Hovold }
1829bd828574SJohan Hovold
dwc3_probe(struct platform_device * pdev)1830c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev)
1831c5ac6116SFelipe Balbi {
1832c5ac6116SFelipe Balbi struct device *dev = &pdev->dev;
183344feb8e6SMasahiro Yamada struct resource *res, dwc_res;
1834c5ac6116SFelipe Balbi void __iomem *regs;
18359a4d7dd1SJohan Hovold struct dwc3 *dwc;
18369a4d7dd1SJohan Hovold int ret;
1837c5ac6116SFelipe Balbi
1838c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1839c5ac6116SFelipe Balbi if (!dwc)
1840c5ac6116SFelipe Balbi return -ENOMEM;
1841c5ac6116SFelipe Balbi
1842c5ac6116SFelipe Balbi dwc->dev = dev;
1843c5ac6116SFelipe Balbi
1844c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1845c5ac6116SFelipe Balbi if (!res) {
1846c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n");
1847c5ac6116SFelipe Balbi return -ENODEV;
1848c5ac6116SFelipe Balbi }
1849c5ac6116SFelipe Balbi
1850c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start;
1851c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1852c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END;
1853c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags;
1854c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name;
1855c5ac6116SFelipe Balbi
1856c5ac6116SFelipe Balbi /*
1857c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs,
1858c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver.
1859c5ac6116SFelipe Balbi */
186044feb8e6SMasahiro Yamada dwc_res = *res;
186144feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START;
186244feb8e6SMasahiro Yamada
1863ec5eb438SStanley Chang if (dev->of_node) {
1864ec5eb438SStanley Chang struct device_node *parent = of_get_parent(dev->of_node);
1865ec5eb438SStanley Chang
1866ec5eb438SStanley Chang if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
1867ec5eb438SStanley Chang dwc_res.start -= DWC3_GLOBALS_REGS_START;
1868ec5eb438SStanley Chang dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
1869ec5eb438SStanley Chang }
1870ec5eb438SStanley Chang
1871ec5eb438SStanley Chang of_node_put(parent);
1872ec5eb438SStanley Chang }
1873ec5eb438SStanley Chang
187444feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res);
187544feb8e6SMasahiro Yamada if (IS_ERR(regs))
187644feb8e6SMasahiro Yamada return PTR_ERR(regs);
1877c5ac6116SFelipe Balbi
1878c5ac6116SFelipe Balbi dwc->regs = regs;
187944feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res);
1880c5ac6116SFelipe Balbi
1881c5ac6116SFelipe Balbi dwc3_get_properties(dwc);
1882c5ac6116SFelipe Balbi
1883babbdfc9SYejune Deng dwc->reset = devm_reset_control_array_get_optional_shared(dev);
18842a735e4bSDan Carpenter if (IS_ERR(dwc->reset)) {
18852a735e4bSDan Carpenter ret = PTR_ERR(dwc->reset);
1886fe296046SJohan Hovold goto err_put_psy;
18872a735e4bSDan Carpenter }
1888fe8abf33SMasahiro Yamada
1889bd828574SJohan Hovold ret = dwc3_get_clocks(dwc);
1890bd828574SJohan Hovold if (ret)
1891fe296046SJohan Hovold goto err_put_psy;
1892fe8abf33SMasahiro Yamada
1893fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset);
1894fe8abf33SMasahiro Yamada if (ret)
1895fe296046SJohan Hovold goto err_put_psy;
1896fe8abf33SMasahiro Yamada
189733fb697eSSean Anderson ret = dwc3_clk_enable(dwc);
1898fe8abf33SMasahiro Yamada if (ret)
1899fe296046SJohan Hovold goto err_assert_reset;
1900fe8abf33SMasahiro Yamada
1901dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) {
1902dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1903dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV;
1904fe296046SJohan Hovold goto err_disable_clks;
1905dc1b5d9aSEnric Balletbo i Serra }
1906dc1b5d9aSEnric Balletbo i Serra
19076c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc);
19082917e718SHeikki Krogerus dwc3_cache_hwparams(dwc);
19096c89cce0SHeikki Krogerus
191091062e66SWilliam Wu if (!dwc->sysdev_is_parent &&
191191062e66SWilliam Wu DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
191291062e66SWilliam Wu ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
191391062e66SWilliam Wu if (ret)
1914fe296046SJohan Hovold goto err_disable_clks;
191591062e66SWilliam Wu }
191691062e66SWilliam Wu
191772246da4SFelipe Balbi spin_lock_init(&dwc->lock);
1918f88359e1SYu Chen mutex_init(&dwc->mutex);
191972246da4SFelipe Balbi
19209a8ad10cSJohan Hovold pm_runtime_get_noresume(dev);
1921fc8bb91bSFelipe Balbi pm_runtime_set_active(dev);
1922fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev);
1923fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1924802ca850SChanho Park pm_runtime_enable(dev);
192532808237SRoger Quadros
1926802ca850SChanho Park pm_runtime_forbid(dev);
192772246da4SFelipe Balbi
19283921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
19293921426bSFelipe Balbi if (ret) {
19303921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n");
19313921426bSFelipe Balbi ret = -ENOMEM;
1932fe296046SJohan Hovold goto err_allow_rpm;
19333921426bSFelipe Balbi }
19343921426bSFelipe Balbi
1935d182c2e1SAndrey Smirnov dwc->edev = dwc3_get_extcon(dwc);
1936d182c2e1SAndrey Smirnov if (IS_ERR(dwc->edev)) {
1937d182c2e1SAndrey Smirnov ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
1938fe296046SJohan Hovold goto err_free_event_buffers;
1939d182c2e1SAndrey Smirnov }
1940d182c2e1SAndrey Smirnov
19419d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc);
19429d6173e1SThinh Nguyen if (ret)
1943fe296046SJohan Hovold goto err_free_event_buffers;
194432a4a135SFelipe Balbi
194572246da4SFelipe Balbi ret = dwc3_core_init(dwc);
194672246da4SFelipe Balbi if (ret) {
19470c0a20f6SAndy Shevchenko dev_err_probe(dev, ret, "failed to initialize core\n");
1948fe296046SJohan Hovold goto err_free_event_buffers;
194972246da4SFelipe Balbi }
195072246da4SFelipe Balbi
19517ac51a12SJohn Youn dwc3_check_params(dwc);
195284524d12SMinas Harutyunyan dwc3_debugfs_init(dwc);
19532c7f1bd9SJohn Youn
19545f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc);
19555f94adfeSFelipe Balbi if (ret)
1956fe296046SJohan Hovold goto err_exit_debugfs;
195772246da4SFelipe Balbi
1958fc8bb91bSFelipe Balbi pm_runtime_put(dev);
195972246da4SFelipe Balbi
19606506e022SRicardo Ribalda dma_set_max_seg_size(dev, UINT_MAX);
19616506e022SRicardo Ribalda
196272246da4SFelipe Balbi return 0;
196372246da4SFelipe Balbi
1964fe296046SJohan Hovold err_exit_debugfs:
196584524d12SMinas Harutyunyan dwc3_debugfs_exit(dwc);
1966f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc);
19671d72fab4SJohan Hovold dwc3_phy_power_off(dwc);
19681d72fab4SJohan Hovold dwc3_phy_exit(dwc);
196908fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc);
1970fe296046SJohan Hovold err_free_event_buffers:
19713921426bSFelipe Balbi dwc3_free_event_buffers(dwc);
1972fe296046SJohan Hovold err_allow_rpm:
19739a8ad10cSJohan Hovold pm_runtime_allow(dev);
19749a8ad10cSJohan Hovold pm_runtime_disable(dev);
19756b3b2402SJohan Hovold pm_runtime_dont_use_autosuspend(dev);
19769a8ad10cSJohan Hovold pm_runtime_set_suspended(dev);
19779a8ad10cSJohan Hovold pm_runtime_put_noidle(dev);
1978fe296046SJohan Hovold err_disable_clks:
197933fb697eSSean Anderson dwc3_clk_disable(dwc);
1980fe296046SJohan Hovold err_assert_reset:
1981fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset);
1982fe296046SJohan Hovold err_put_psy:
1983b0bf77cdSColin Ian King if (dwc->usb_psy)
19846f0764b5SRay Chi power_supply_put(dwc->usb_psy);
19856f0764b5SRay Chi
198672246da4SFelipe Balbi return ret;
198772246da4SFelipe Balbi }
198872246da4SFelipe Balbi
dwc3_remove(struct platform_device * pdev)198901765687SUwe Kleine-König static void dwc3_remove(struct platform_device *pdev)
199072246da4SFelipe Balbi {
199172246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev);
19923da1f6eeSFelipe Balbi
1993fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev);
199472246da4SFelipe Balbi
1995dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc);
19962a042767SPeter Chen dwc3_debugfs_exit(dwc);
19978ba007a9SKishon Vijay Abraham I
199872246da4SFelipe Balbi dwc3_core_exit(dwc);
199988bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc);
200072246da4SFelipe Balbi
200144d257e9SJohan Hovold pm_runtime_allow(&pdev->dev);
2002fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev);
20036b3b2402SJohan Hovold pm_runtime_dont_use_autosuspend(&pdev->dev);
2004266d0493SLi Jun pm_runtime_put_noidle(&pdev->dev);
2005e3dbb657SJohan Hovold /*
2006e3dbb657SJohan Hovold * HACK: Clear the driver data, which is currently accessed by parent
2007e3dbb657SJohan Hovold * glue drivers, before allowing the parent to suspend.
2008e3dbb657SJohan Hovold */
2009e3dbb657SJohan Hovold platform_set_drvdata(pdev, NULL);
2010266d0493SLi Jun pm_runtime_set_suspended(&pdev->dev);
2011fc8bb91bSFelipe Balbi
2012c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc);
2013c499ff71SFelipe Balbi
2014b0bf77cdSColin Ian King if (dwc->usb_psy)
20156f0764b5SRay Chi power_supply_put(dwc->usb_psy);
201672246da4SFelipe Balbi }
201772246da4SFelipe Balbi
2018fc8bb91bSFelipe Balbi #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)2019fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2020fe8abf33SMasahiro Yamada {
2021fe8abf33SMasahiro Yamada int ret;
2022fe8abf33SMasahiro Yamada
2023fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset);
2024fe8abf33SMasahiro Yamada if (ret)
2025fe8abf33SMasahiro Yamada return ret;
2026fe8abf33SMasahiro Yamada
202733fb697eSSean Anderson ret = dwc3_clk_enable(dwc);
2028fe8abf33SMasahiro Yamada if (ret)
2029fe8abf33SMasahiro Yamada goto assert_reset;
2030fe8abf33SMasahiro Yamada
2031fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc);
2032fe8abf33SMasahiro Yamada if (ret)
2033fe8abf33SMasahiro Yamada goto disable_clks;
2034fe8abf33SMasahiro Yamada
2035fe8abf33SMasahiro Yamada return 0;
2036fe8abf33SMasahiro Yamada
2037fe8abf33SMasahiro Yamada disable_clks:
203833fb697eSSean Anderson dwc3_clk_disable(dwc);
2039fe8abf33SMasahiro Yamada assert_reset:
2040fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset);
2041fe8abf33SMasahiro Yamada
2042fe8abf33SMasahiro Yamada return ret;
2043fe8abf33SMasahiro Yamada }
2044fe8abf33SMasahiro Yamada
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)2045c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
20467415f17cSFelipe Balbi {
2047fc8bb91bSFelipe Balbi unsigned long flags;
2048bcb12877SManu Gautam u32 reg;
20497415f17cSFelipe Balbi
2050689bf72cSManu Gautam switch (dwc->current_dr_role) {
2051689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE:
20520227cc84SLi Jun if (pm_runtime_suspended(dwc->dev))
20530227cc84SLi Jun break;
20547415f17cSFelipe Balbi dwc3_gadget_suspend(dwc);
205541a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget);
2056689bf72cSManu Gautam dwc3_core_exit(dwc);
205751f5d49aSFelipe Balbi break;
2058689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST:
2059e3fafbd8SJohan Hovold if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2060c4a5153eSManu Gautam dwc3_core_exit(dwc);
2061c4a5153eSManu Gautam break;
2062bcb12877SManu Gautam }
2063bcb12877SManu Gautam
2064bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */
2065bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk ||
2066bcb12877SManu Gautam dwc->dis_enblslpm_quirk) {
2067bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2068bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2069bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY;
2070bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2071bcb12877SManu Gautam
2072bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */
2073bcb12877SManu Gautam usleep_range(5000, 6000);
2074bcb12877SManu Gautam }
2075bcb12877SManu Gautam
2076bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2077bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
2078bcb12877SManu Gautam break;
2079f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG:
2080f09cc79bSRoger Quadros /* do nothing during runtime_suspend */
2081f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg))
2082f09cc79bSRoger Quadros break;
2083f09cc79bSRoger Quadros
2084f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2085f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags);
2086f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc);
2087f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags);
208841a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget);
2089f09cc79bSRoger Quadros }
2090f09cc79bSRoger Quadros
2091f09cc79bSRoger Quadros dwc3_otg_exit(dwc);
2092f09cc79bSRoger Quadros dwc3_core_exit(dwc);
2093f09cc79bSRoger Quadros break;
20947415f17cSFelipe Balbi default:
209551f5d49aSFelipe Balbi /* do nothing */
20967415f17cSFelipe Balbi break;
20977415f17cSFelipe Balbi }
20987415f17cSFelipe Balbi
2099fc8bb91bSFelipe Balbi return 0;
2100fc8bb91bSFelipe Balbi }
2101fc8bb91bSFelipe Balbi
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)2102c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2103fc8bb91bSFelipe Balbi {
2104fc8bb91bSFelipe Balbi unsigned long flags;
2105fc8bb91bSFelipe Balbi int ret;
2106bcb12877SManu Gautam u32 reg;
2107fc8bb91bSFelipe Balbi
2108689bf72cSManu Gautam switch (dwc->current_dr_role) {
2109689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE:
2110fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc);
2111fc8bb91bSFelipe Balbi if (ret)
2112fc8bb91bSFelipe Balbi return ret;
2113fc8bb91bSFelipe Balbi
21147d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2115fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc);
2116689bf72cSManu Gautam break;
2117689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST:
2118e3fafbd8SJohan Hovold if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2119fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc);
2120c4a5153eSManu Gautam if (ret)
2121c4a5153eSManu Gautam return ret;
21227d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2123bcb12877SManu Gautam break;
2124c4a5153eSManu Gautam }
2125bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */
2126bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2127bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk)
2128bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2129bcb12877SManu Gautam
2130bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk)
2131bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2132bcb12877SManu Gautam
2133bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2134bcb12877SManu Gautam
2135bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2136bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2137c4a5153eSManu Gautam break;
2138f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG:
2139f09cc79bSRoger Quadros /* nothing to do on runtime_resume */
2140f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg))
2141f09cc79bSRoger Quadros break;
2142f09cc79bSRoger Quadros
21430e5a3c82SGary Bisson ret = dwc3_core_init_for_resume(dwc);
2144f09cc79bSRoger Quadros if (ret)
2145f09cc79bSRoger Quadros return ret;
2146f09cc79bSRoger Quadros
2147f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role);
2148f09cc79bSRoger Quadros
2149f09cc79bSRoger Quadros dwc3_otg_init(dwc);
2150f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2151f09cc79bSRoger Quadros dwc3_otg_host_init(dwc);
2152f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2153f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags);
2154f09cc79bSRoger Quadros dwc3_gadget_resume(dwc);
2155f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags);
2156f09cc79bSRoger Quadros }
2157f09cc79bSRoger Quadros
2158f09cc79bSRoger Quadros break;
2159fc8bb91bSFelipe Balbi default:
2160fc8bb91bSFelipe Balbi /* do nothing */
2161fc8bb91bSFelipe Balbi break;
2162fc8bb91bSFelipe Balbi }
2163fc8bb91bSFelipe Balbi
2164fc8bb91bSFelipe Balbi return 0;
2165fc8bb91bSFelipe Balbi }
2166fc8bb91bSFelipe Balbi
dwc3_runtime_checks(struct dwc3 * dwc)2167fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc)
2168fc8bb91bSFelipe Balbi {
2169689bf72cSManu Gautam switch (dwc->current_dr_role) {
2170c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE:
2171fc8bb91bSFelipe Balbi if (dwc->connected)
2172fc8bb91bSFelipe Balbi return -EBUSY;
2173fc8bb91bSFelipe Balbi break;
2174c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST:
2175fc8bb91bSFelipe Balbi default:
2176fc8bb91bSFelipe Balbi /* do nothing */
2177fc8bb91bSFelipe Balbi break;
2178fc8bb91bSFelipe Balbi }
2179fc8bb91bSFelipe Balbi
2180fc8bb91bSFelipe Balbi return 0;
2181fc8bb91bSFelipe Balbi }
2182fc8bb91bSFelipe Balbi
dwc3_runtime_suspend(struct device * dev)2183fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev)
2184fc8bb91bSFelipe Balbi {
2185fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev);
2186fc8bb91bSFelipe Balbi int ret;
2187fc8bb91bSFelipe Balbi
2188fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc))
2189fc8bb91bSFelipe Balbi return -EBUSY;
2190fc8bb91bSFelipe Balbi
2191c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2192fc8bb91bSFelipe Balbi if (ret)
2193fc8bb91bSFelipe Balbi return ret;
2194fc8bb91bSFelipe Balbi
2195fc8bb91bSFelipe Balbi return 0;
2196fc8bb91bSFelipe Balbi }
2197fc8bb91bSFelipe Balbi
dwc3_runtime_resume(struct device * dev)2198fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev)
2199fc8bb91bSFelipe Balbi {
2200fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev);
2201fc8bb91bSFelipe Balbi int ret;
2202fc8bb91bSFelipe Balbi
2203c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2204fc8bb91bSFelipe Balbi if (ret)
2205fc8bb91bSFelipe Balbi return ret;
2206fc8bb91bSFelipe Balbi
2207689bf72cSManu Gautam switch (dwc->current_dr_role) {
2208689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE:
2209fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc);
2210fc8bb91bSFelipe Balbi break;
2211689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST:
2212fc8bb91bSFelipe Balbi default:
2213fc8bb91bSFelipe Balbi /* do nothing */
2214fc8bb91bSFelipe Balbi break;
2215fc8bb91bSFelipe Balbi }
2216fc8bb91bSFelipe Balbi
2217fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev);
2218fc8bb91bSFelipe Balbi
2219fc8bb91bSFelipe Balbi return 0;
2220fc8bb91bSFelipe Balbi }
2221fc8bb91bSFelipe Balbi
dwc3_runtime_idle(struct device * dev)2222fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev)
2223fc8bb91bSFelipe Balbi {
2224fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev);
2225fc8bb91bSFelipe Balbi
2226689bf72cSManu Gautam switch (dwc->current_dr_role) {
2227689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE:
2228fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc))
2229fc8bb91bSFelipe Balbi return -EBUSY;
2230fc8bb91bSFelipe Balbi break;
2231689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST:
2232fc8bb91bSFelipe Balbi default:
2233fc8bb91bSFelipe Balbi /* do nothing */
2234fc8bb91bSFelipe Balbi break;
2235fc8bb91bSFelipe Balbi }
2236fc8bb91bSFelipe Balbi
2237fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev);
2238fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev);
2239fc8bb91bSFelipe Balbi
2240fc8bb91bSFelipe Balbi return 0;
2241fc8bb91bSFelipe Balbi }
2242fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */
2243fc8bb91bSFelipe Balbi
2244fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)2245fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev)
2246fc8bb91bSFelipe Balbi {
2247fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev);
2248fc8bb91bSFelipe Balbi int ret;
2249fc8bb91bSFelipe Balbi
2250c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2251fc8bb91bSFelipe Balbi if (ret)
2252fc8bb91bSFelipe Balbi return ret;
2253fc8bb91bSFelipe Balbi
22546344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev);
22556344475fSSekhar Nori
22567415f17cSFelipe Balbi return 0;
22577415f17cSFelipe Balbi }
22587415f17cSFelipe Balbi
dwc3_resume(struct device * dev)22597415f17cSFelipe Balbi static int dwc3_resume(struct device *dev)
22607415f17cSFelipe Balbi {
22617415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev);
226257303488SKishon Vijay Abraham I int ret;
22637415f17cSFelipe Balbi
22646344475fSSekhar Nori pinctrl_pm_select_default_state(dev);
22656344475fSSekhar Nori
2266c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME);
226751f5d49aSFelipe Balbi if (ret)
22685c4ad318SFelipe Balbi return ret;
22695c4ad318SFelipe Balbi
22707415f17cSFelipe Balbi pm_runtime_disable(dev);
22717415f17cSFelipe Balbi pm_runtime_set_active(dev);
22727415f17cSFelipe Balbi pm_runtime_enable(dev);
22737415f17cSFelipe Balbi
22747415f17cSFelipe Balbi return 0;
22757415f17cSFelipe Balbi }
2276f580170fSYu Chen
dwc3_complete(struct device * dev)2277f580170fSYu Chen static void dwc3_complete(struct device *dev)
2278f580170fSYu Chen {
2279f580170fSYu Chen struct dwc3 *dwc = dev_get_drvdata(dev);
2280f580170fSYu Chen u32 reg;
2281f580170fSYu Chen
2282f580170fSYu Chen if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2283f580170fSYu Chen dwc->dis_split_quirk) {
2284f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2285f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE;
2286f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2287f580170fSYu Chen }
2288f580170fSYu Chen }
2289f580170fSYu Chen #else
2290f580170fSYu Chen #define dwc3_complete NULL
22917f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */
22927415f17cSFelipe Balbi
22937415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = {
22947415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2295f580170fSYu Chen .complete = dwc3_complete,
2296fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2297fc8bb91bSFelipe Balbi dwc3_runtime_idle)
22987415f17cSFelipe Balbi };
22997415f17cSFelipe Balbi
23005088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF
23015088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = {
23025088b6f5SKishon Vijay Abraham I {
230322a5aa17SFelipe Balbi .compatible = "snps,dwc3"
230422a5aa17SFelipe Balbi },
230522a5aa17SFelipe Balbi {
23065088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3"
23075088b6f5SKishon Vijay Abraham I },
23085088b6f5SKishon Vijay Abraham I { },
23095088b6f5SKishon Vijay Abraham I };
23105088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match);
23115088b6f5SKishon Vijay Abraham I #endif
23125088b6f5SKishon Vijay Abraham I
2313404905a6SHeikki Krogerus #ifdef CONFIG_ACPI
2314404905a6SHeikki Krogerus
2315404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7"
2316404905a6SHeikki Krogerus
2317404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = {
2318404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 },
2319404905a6SHeikki Krogerus { },
2320404905a6SHeikki Krogerus };
2321404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2322404905a6SHeikki Krogerus #endif
2323404905a6SHeikki Krogerus
232472246da4SFelipe Balbi static struct platform_driver dwc3_driver = {
232572246da4SFelipe Balbi .probe = dwc3_probe,
232601765687SUwe Kleine-König .remove_new = dwc3_remove,
232772246da4SFelipe Balbi .driver = {
232872246da4SFelipe Balbi .name = "dwc3",
23295088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match),
2330404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
23317f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops,
233272246da4SFelipe Balbi },
233372246da4SFelipe Balbi };
233472246da4SFelipe Balbi
2335b1116dccSTobias Klauser module_platform_driver(dwc3_driver);
2336b1116dccSTobias Klauser
23377ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3");
233872246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
23395945f789SFelipe Balbi MODULE_LICENSE("GPL v2");
234072246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2341