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/openbmc/linux/drivers/infiniband/hw/mlx5/
H A Dqpc.c13 struct mlx5_core_dct *dct);
93 struct mlx5_core_dct *dct; in dct_event_notifier() local
97 qpn = be32_to_cpu(eqe->data.dct.dctn) & 0xFFFFFF; in dct_event_notifier()
99 dct = xa_load(&dev->qp_table.dct_xa, qpn); in dct_event_notifier()
100 if (dct) in dct_event_notifier()
101 complete(&dct->drained); in dct_event_notifier()
196 struct mlx5_core_dct *dct) in _mlx5_core_destroy_dct() argument
199 struct mlx5_core_qp *qp = &dct->mqp; in _mlx5_core_destroy_dct()
207 int mlx5_core_create_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct, in mlx5_core_create_dct() argument
210 struct mlx5_core_qp *qp = &dct->mqp; in mlx5_core_create_dct()
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H A Dqp.h31 int mlx5_core_destroy_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct);
34 int mlx5_core_dct_query(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct,
H A Dqp.c2741 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); in create_dct()
2742 if (!qp->dct.in) in create_dct()
2745 MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); in create_dct()
2746 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); in create_dct()
2769 if (attr->qp_type == IB_QPT_DRIVER && !MLX5_CAP_GEN(dev->mdev, dct)) in check_qp_type()
3195 err = mlx5_core_destroy_dct(dev, &mqp->dct.mdct); in mlx5_ib_destroy_dct()
3197 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); in mlx5_ib_destroy_dct()
3202 kfree(mqp->dct.in); in mlx5_ib_destroy_dct()
4488 /* mlx5_ib_modify_dct: modify a DCT QP
4512 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); in mlx5_ib_modify_dct()
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/openbmc/linux/drivers/media/platform/verisilicon/
H A Dhantro_g1_vp8_dec.c18 /* DCT partition base address regs */
71 /* DCT partition start bits regs */
207 * set control partition and DCT partition regs
217 * | tag 3B | extra 7B | hdr | mb_data | DCT sz | DCT part0 | ... | DCT partn |
223 * DCT size part
228 * 3. number of DCT parts is 1, 2, 4 or 8
285 * Calculate DCT partition info in cfg_parts()
286 * @dct_size_part_size: Containing sizes of DCT part, every DCT part in cfg_parts()
288 * DCT part in cfg_parts()
289 * @dct_part_offset: bytes offset of DCT parts from src_dma base addr in cfg_parts()
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H A Drockchip_vpu2_hw_vp8_dec.c387 * Calculate DCT partition info in cfg_parts()
388 * @dct_size_part_size: Containing sizes of DCT part, every DCT part in cfg_parts()
390 * DCT part in cfg_parts()
391 * @dct_part_offset: bytes offset of DCT parts from src_dma base addr in cfg_parts()
392 * @dct_part_total_len: total size of all DCT parts in cfg_parts()
401 /* Number of DCT partitions */ in cfg_parts()
405 /* DCT partition length */ in cfg_parts()
408 /* DCT partitions base address */ in cfg_parts()
/openbmc/linux/drivers/edac/
H A Damd64_edac.c100 * Select DCT to which PCI cfg accesses are routed
102 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
108 reg |= dct; in f15h_select_dct()
114 * Depending on the family, F2 DCT reads need special handling:
116 * K8: has a single DCT only and no address offsets >= 0x100
118 * F10h: each DCT has its own set of regs
122 * F16h: has only 1 DCT
124 * F15h: we select which DCT we access using F1x10C[DctCfgSel]
126 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
131 if (dct || offse in amd64_read_dct_pci_cfg()
372 get_cs_base_and_mask(struct amd64_pvt * pvt,int csrow,u8 dct,u64 * base,u64 * mask) get_cs_base_and_mask() argument
428 for_each_chip_select(i,dct,pvt) global() argument
431 chip_select_base(i,dct,pvt) global() argument
434 for_each_chip_select_mask(i,dct,pvt) global() argument
2113 k8_dbam_to_chip_select(struct amd64_pvt * pvt,u8 dct,unsigned cs_mode,int cs_mask_nr) k8_dbam_to_chip_select() argument
2217 f10_dbam_to_chip_select(struct amd64_pvt * pvt,u8 dct,unsigned cs_mode,int cs_mask_nr) f10_dbam_to_chip_select() argument
2233 f15_dbam_to_chip_select(struct amd64_pvt * pvt,u8 dct,unsigned cs_mode,int cs_mask_nr) f15_dbam_to_chip_select() argument
2242 f15_m60h_dbam_to_chip_select(struct amd64_pvt * pvt,u8 dct,unsigned cs_mode,int cs_mask_nr) f15_m60h_dbam_to_chip_select() argument
2275 f16_dbam_to_chip_select(struct amd64_pvt * pvt,u8 dct,unsigned cs_mode,int cs_mask_nr) f16_dbam_to_chip_select() argument
2447 f10_process_possible_spare(struct amd64_pvt * pvt,u8 dct,int csrow) f10_process_possible_spare() argument
2472 f1x_lookup_addr_in_dct(u64 in_addr,u8 nid,u8 dct) f1x_lookup_addr_in_dct() argument
3291 dct_get_csrow_nr_pages(struct amd64_pvt * pvt,u8 dct,int csrow_nr) dct_get_csrow_nr_pages() argument
3309 umc_get_csrow_nr_pages(struct amd64_pvt * pvt,u8 dct,int csrow_nr_orig) umc_get_csrow_nr_pages() argument
3824 gpu_get_csrow_nr_pages(struct amd64_pvt * pvt,u8 dct,int csrow_nr) gpu_get_csrow_nr_pages() argument
4226 int cs = 0, dct = 0; instance_has_memory() local
[all...]
H A Damd64_edac.h166 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) argument
167 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE) argument
296 /* A DCT chip selects collection */
353 /* one for each DCT/UMC */
467 int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct,
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/libtevent/libtevent/
H A D0002-Fix-pyext_PATTERN-for-cross-compilation.patch33 if dct[x]:
34 env[x] = conf.environ[x] = str(dct[x])
35 - env.pyext_PATTERN = '%s' + (dct['EXT_SUFFIX'] or dct['SO']) # SO is deprecated in 3.5 and removed…
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/libtdb/libtdb/
H A D0002-Fix-pyext_PATTERN-for-cross-compilation.patch33 if dct[x]:
34 env[x] = conf.environ[x] = str(dct[x])
35 - env.pyext_PATTERN = '%s' + (dct['EXT_SUFFIX'] or dct['SO']) # SO is deprecated in 3.5 and removed…
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/libtalloc/libtalloc/
H A D0002-Fix-pyext_PATTERN-for-cross-compilation.patch48 if dct[x]:
49 env[x] = conf.environ[x] = str(dct[x])
50 - env.pyext_PATTERN = '%s' + (dct['EXT_SUFFIX'] or dct['SO']) # SO is deprecated in 3.5 and removed…
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/libldb/libldb/
H A D0003-Fix-pyext_PATTERN-for-cross-compilation.patch50 if dct[x]:
51 env[x] = conf.environ[x] = str(dct[x])
52 - env.pyext_PATTERN = '%s' + (dct['EXT_SUFFIX'] or dct['SO']) # SO is deprecated in 3.5 and removed…
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-connectivity/samba/samba/
H A D0005-Fix-pyext_PATTERN-for-cross-compilation.patch54 if dct[x]:
55 env[x] = conf.environ[x] = str(dct[x])
56 - env.pyext_PATTERN = '%s' + (dct['EXT_SUFFIX'] or dct['SO']) # SO is deprecated in 3.5 and removed…
/openbmc/linux/drivers/media/v4l2-core/
H A Dv4l2-jpeg.c175 * Baseline DCT only supports 8-bit precision. in jpeg_parse_frame_header()
176 * Extended sequential DCT also supports 12-bit precision. in jpeg_parse_frame_header()
312 /* Lq = 2 + n * 65 (for baseline DCT), n >= 1 */ in jpeg_parse_quantization_tables()
329 * sequential DCT with 12-bit sample precision also supports in jpeg_parse_quantization_tables()
385 /* only two Huffman tables for baseline DCT */ in jpeg_parse_huffman_tables()
516 /* baseline DCT, extended sequential DCT */ in v4l2_jpeg_parse_header()
/openbmc/linux/drivers/i3c/master/mipi-i3c-hci/
H A Ddct.h7 * Common DCT related stuff
H A Ddct_v1.c14 #include "dct.h"
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/epeg/
H A Depeg_git.bb2 …se of libjpeg features of being able to load an image by only decoding the DCT coefficients needed…
/openbmc/linux/drivers/media/pci/bt8xx/
H A Ddst.c463 } else if (!strncmp(state->fw_name, "DCT-CI", 6)) { in dst_set_symbolrate()
495 else if (!strncmp(state->fw_name, "DCT-CI", 6)) in dst_set_modulation()
644 .fw_name = "DCT-CI"
651 .fw_name = "DCT-CI"
658 .fw_name = "DCT-CI"
720 VP-2030 DCT-CI, Samsung, TS=204
721 VP-2021 DCT-CI, Unknown, TS=204
722 VP-2031 DCT-CI, Philips, TS=188
723 VP-2040 DCT-CI, Philips, TS=188, with CA daughter board
724 VP-2040 DCT-CI, Philips, TS=204, without CA daughter board
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dnxp,imx8-jpeg.yaml15 and Extended Sequential DCT modes.
/openbmc/u-boot/board/freescale/mx31pdk/
H A Dmx31pdk.c60 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ in board_early_init_f()
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-jpeg.rst11 progressive baseline DCT compression process with Huffman entropy
/openbmc/linux/Documentation/admin-guide/media/
H A Divtv-cardlist.rst86 - Digital Cowboy DCT-MTVP1
/openbmc/qemu/target/s390x/
H A Dioinst.c730 int dct; in ioinst_handle_schm() local
742 dct = SCHM_REG1_DCT(reg1); in ioinst_handle_schm()
749 css_do_schm(mbk, update, dct, update ? reg2 : 0); in ioinst_handle_schm()
/openbmc/linux/drivers/soc/fsl/dpio/
H A Dqbman-portal.c1065 * @dct: the dequeue command type
1068 enum qbman_pull_type_e dct) in qbman_pull_desc_set_wq() argument
1070 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT; in qbman_pull_desc_set_wq()
1080 * @dct: the dequeue command type
1083 enum qbman_pull_type_e dct) in qbman_pull_desc_set_channel() argument
1085 d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT; in qbman_pull_desc_set_channel()
H A Dqbman-portal.h215 enum qbman_pull_type_e dct);
217 enum qbman_pull_type_e dct);
/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Dimx-regs.h495 #define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \ argument
499 (dww) << 6 | (dct) << 4 | (wwu) << 3 |\

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