Home
last modified time | relevance | path

Searched +full:cortex +full:- +full:a9 (Results 1 – 25 of 243) sorted by relevance

12345678910

/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
28 - arm,cortex-a9-scu
29 - arm,cortex-a5-scu
[all …]
/openbmc/linux/arch/arm/boot/dts/calxeda/
H A Dhighbank.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a9";
25 next-level-cache = <&L2>;
27 clock-names = "cpu";
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca9.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A9 MPCore (V2P-CA9)
8 * HBI-0191B
11 /dts-v1/;
12 #include "vexpress-v2m.dtsi"
15 model = "V2P-CA9";
18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
H A Darm-realview-eb-a9mp.dts23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
27 model = "ARM RealView EB Cortex A9 MPCore";
30 * This is the Cortex A9 MPCore tile used with the
34 #address-cells = <1>;
35 #size-cells = <0>;
36 enable-method = "arm,realview-smp";
40 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
[all …]
H A Darm-realview-pbx-a9.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/cpu-enable-method/
H A Dnuvoton,npcm750-smp2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
[all …]
/openbmc/linux/arch/arm/boot/dts/actions/
H A Dowl-s500.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (c) 2016-2017 Andreas Färber
8 #include <dt-bindings/clock/actions,s500-cmu.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/owl-s500-powergate.h>
12 #include <dt-bindings/reset/actions,s500-reset.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-dt.txt11 - None
14 - operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for
17 - clock-latency: Specify the possible maximum transition latency for clock,
19 - voltage-tolerance: Specify the CPU voltage tolerance in percentage.
20 - #cooling-cells:
22 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,global_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stuart Menefy <stuart.menefy@st.com>
13 Cortex-A9 are often associated with a per-core Global timer.
18 - enum:
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
34 - compatible
35 - reg
[all …]
H A Darm,twd-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Timer
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-timer
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
[all …]
/openbmc/linux/arch/arm/mach-bcm/
H A Dbcm63xx_smp.c1 // SPDX-License-Identifier: GPL-2.0-only
22 /* Size of mapped Cortex A9 SCU address space */
26 * Enable the Cortex A9 Snoop Control Unit
29 * cores present. We assume we're running on a Cortex A9 processor,
43 return -ENXIO; in scu_a9_enable()
50 return -ENOENT; in scu_a9_enable()
57 return -ENOMEM; in scu_a9_enable()
70 /* The BCM63138 SoC has two Cortex-A9 CPUs, CPU0 features a complete in scu_a9_enable()
72 * Since we will not be able to trap kernel-mode NEON to force in scu_a9_enable()
76 * all, for kernel-mode NEON, we do not want to introduce any in scu_a9_enable()
[all …]
/openbmc/qemu/docs/system/arm/
H A Dxlnx-zynq.rst1 Xilinx Zynq board (``xilinx-zynq-a9``)
4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
10 QEMU xilinx-zynq-a9 board supports following devices:
11 - A9 MPCORE
12 - cortex-a9
13 - GIC v1
14 - Generic timer
15 - wdt
16 - OCM 256KB
[all …]
H A Dnuvoton.rst1 Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj`…
4 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
6 servers. They all feature one or two ARM Cortex-A9 CPU cores, as well as an
11 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
13 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
16 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
18 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
21 - ``quanta-gbs-bmc`` Quanta GBS server BMC
22 - ``quanta-gsj`` Quanta GSJ server BMC
23 - ``kudo-bmc`` Fii USA Kudo server BMC
[all …]
H A Drealview.rst1 Arm Realview boards (``realview-eb``, ``realview-eb-mpcore``, ``realview-pb-a8``, ``realview-pbx-a9…
5 the EB, PB-A8 and PBX-A9. Due to interactions with the bootloader, only
8 Kernels for the PB-A8 board should have CONFIG_REALVIEW_HIGH_PHYS_OFFSET
9 enabled in the kernel, and expect 512M RAM. Kernels for The PBX-A9 board
15 - ARM926E, ARM1136, ARM11MPCore, Cortex-A8 or Cortex-A9 MPCore CPU
17 - Arm AMBA Generic/Distributed Interrupt Controller
19 - Four PL011 UARTs
21 - SMC 91c111 or SMSC LAN9118 Ethernet adapter
23 - PL110 LCD controller
25 - PL050 KMI with PS/2 keyboard and mouse
[all …]
/openbmc/linux/arch/arm/boot/dts/nuvoton/
H A Dnuvoton-npcm730.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "nuvoton-common-npcm7xx.dtsi"
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&gic>;
12 #address-cells = <1>;
13 #size-cells = <0>;
14 enable-method = "nuvoton,npcm750-smp";
18 compatible = "arm,cortex-a9";
20 clock-names = "clk_cpu";
[all …]
H A Dnuvoton-npcm750.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include "nuvoton-common-npcm7xx.dtsi"
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
13 #address-cells = <1>;
14 #size-cells = <0>;
15 enable-method = "nuvoton,npcm750-smp";
19 compatible = "arm,cortex-a9";
21 clock-names = "clk_cpu";
[all …]
/openbmc/qemu/hw/cpu/
H A Da9mpcore.c2 * Cortex-A9MPCore internal peripheral emulation.
16 #include "hw/qdev-properties.h"
18 #include "target/arm/cpu-qom.h"
26 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in a9mp_priv_set_irq()
33 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); in a9mp_priv_initfn()
34 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); in a9mp_priv_initfn()
36 object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU); in a9mp_priv_initfn()
38 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in a9mp_priv_initfn()
40 object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER); in a9mp_priv_initfn()
42 object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); in a9mp_priv_initfn()
[all …]
/openbmc/u-boot/doc/
H A DREADME.rmobile4 This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
5 and Cortex-A9/A53/A57 based R-Car[2] family of SoCs. Renesas's RMOBILE/R-Car SoC
6 family contains an ARM Cortex-A9/A53/A57.
12 | R8A73A0 | KMC KZM-A9-GT [3] | kzm9g_config
13 | R8A7734 | Atmark-Techno Armadillo-800-EVA [4] | armadillo-800eva_config
17 |---------------+----------------------------------------+-------------------
18 | R8A7791 M2-W | Renesas Electronics Koelsch | koelsch_defconfig
20 |---------------+----------------------------------------+-------------------
22 |---------------+----------------------------------------+-------------------
23 | R8A7793 M2-N | Renesas Electronics Gose | gose_defconfig
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Darm,twd-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Watchdog
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-wdt
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/ux500/
H A Dboards.txt1 ST-Ericsson Ux500 boards
2 ------------------------
5 compatible = "st-ericsson,mop500" (legacy)
6 compatible = "st-ericsson,u8500"
10 soc: represents the system-on-chip and contains the chip
20 compatible = "ste,dbx500-backupram"
25 interrupt-controller:
26 see binding for interrupt-controller/arm,gic.txt
29 see binding for timer/arm,twd-timer.yaml
36 /dts-v1/;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf500.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a5";
28 intc: interrupt-controller@40003000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear13xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a9";
21 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
[all …]
/openbmc/linux/arch/arm/mach-zynq/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 bool "Xilinx Zynq ARM Cortex A9 Platform"
17 Support for Xilinx Zynq ARM Cortex A9 Platform

12345678910