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/openbmc/linux/drivers/clk/mediatek/
H A DKconfig27 This driver supports MediaTek MT2701 basic clocks.
33 This driver supports MediaTek MT2701 mmsys clocks.
39 This driver supports MediaTek MT2701 imgsys clocks.
45 This driver supports MediaTek MT2701 vdecsys clocks.
51 This driver supports MediaTek MT2701 hifsys clocks.
57 This driver supports MediaTek MT2701 ethsys clocks.
63 This driver supports MediaTek MT2701 bdpsys clocks.
69 This driver supports Mediatek MT2701 audsys clocks.
75 This driver supports MediaTek MT2701 g3dsys clocks.
83 This driver supports MediaTek MT2712 basic clocks.
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-clk-ccf.dtsi54 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
62 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
66 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
70 clocks = <&zynqmp_clk ACPU>;
74 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
78 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
82 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
86 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
90 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
94 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210.dtsi82 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
94 clocks: clock-controller@e0100000 { label
98 clocks = <&xxti>, <&xusbxti>;
125 clocks = <&clocks CLK_PDMA0>;
135 clocks = <&clocks CLK_PDMA1>;
145 clocks = <&clocks CLK_TSADC>;
158 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
174 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
188 clocks = <&clocks CLK_KEYIF>;
198 clocks = <&clocks CLK_I2C0>;
[all …]
H A Ds3c64xx.dtsi68 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
69 <&clocks SCLK_MMC0>;
79 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
80 <&clocks SCLK_MMC1>;
90 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
91 <&clocks SCLK_MMC2>;
101 clocks = <&clocks PCLK_WDT>;
110 clocks = <&clocks PCLK_IIC0>;
123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
124 <&clocks SCLK_UART>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-clk-ccf.dtsi14 clocks = <&clkc 71>;
20 clocks = <&clkc 72>;
26 clocks = <&clkc 73>;
32 clocks = <&clkc 74>;
74 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
108 clocks = <&clkc 63>, <&clkc 31>;
112 clocks = <&clkc 64>, <&clkc 31>;
116 clocks = <&clkc 10>;
120 clocks = <&clkc 19>, <&clkc 31>;
124 clocks = <&clkc 19>, <&clkc 31>;
[all …]
H A Dzynqmp-clk.dtsi78 clocks = <&clk100 &clk100>;
82 clocks = <&clk100 &clk100>;
86 clocks = <&clk600>, <&clk100>;
90 clocks = <&clk600>, <&clk100>;
94 clocks = <&clk600>, <&clk100>;
98 clocks = <&clk600>, <&clk100>;
102 clocks = <&clk600>, <&clk100>;
106 clocks = <&clk600>, <&clk100>;
110 clocks = <&clk600>, <&clk100>;
114 clocks = <&clk600>, <&clk100>;
[all …]
H A Domap3xxx-clocks.dtsi20 …clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck…
27 clocks = <&osc_sys_ck>;
37 clocks = <&osc_sys_ck>;
45 clocks = <&dpll3_ck>;
53 clocks = <&dpll3_m2_ck>;
61 clocks = <&dpll4_ck>;
69 clocks = <&dpll3_m2x2_ck>;
77 clocks = <&sys_ck>;
87 clocks = <&core_96m_fck>, <&mcbsp_clks>;
95 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
[all …]
H A Dam43xx-clocks.dtsi14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
22 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
30 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
38 clocks = <&sys_clkin_ck>;
46 clocks = <&sys_clkin_ck>;
54 clocks = <&sys_clkin_ck>;
62 clocks = <&sys_clkin_ck>;
70 clocks = <&sys_clkin_ck>;
78 clocks = <&sys_clkin_ck>;
86 clocks = <&sys_clkin_ck>;
[all …]
H A Ddra7xx-clocks.dtsi14 clocks = <&atl_gfclk_mux>;
20 clocks = <&atl_gfclk_mux>;
26 clocks = <&atl_gfclk_mux>;
32 clocks = <&atl_gfclk_mux>;
110 clocks = <&sys_clkin1>;
202 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
209 clocks = <&dpll_abe_ck>;
215 clocks = <&dpll_abe_x2_ck>;
226 clocks = <&dpll_abe_m2x2_ck>;
235 clocks = <&dpll_abe_ck>;
[all …]
H A Dam33xx-clocks.dtsi14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
22 clocks = <&sys_clkin_ck>;
30 clocks = <&sys_clkin_ck>;
38 clocks = <&sys_clkin_ck>;
46 clocks = <&sys_clkin_ck>;
54 clocks = <&sys_clkin_ck>;
62 clocks = <&sys_clkin_ck>;
70 clocks = <&sys_clkin_ck>;
78 clocks = <&sys_clkin_ck>;
86 clocks = <&sys_clkin_ck>;
[all …]
H A Dsocfpga.dtsi85 clocks = <&l4_main_clk>;
102 clocks = <&can0_clk>;
110 clocks = <&can1_clk>;
118 clocks {
147 clocks = <&osc1>;
153 clocks = <&main_pll>;
161 clocks = <&main_pll>;
169 clocks = <&main_pll>, <&osc1>;
177 clocks = <&main_pll>;
184 clocks = <&main_pll>;
[all …]
H A Domap34xx-omap36xx-clocks.dtsi14 clocks = <&l4_ick>;
22 clocks = <&security_l4_ick2>;
30 clocks = <&security_l4_ick2>;
38 clocks = <&security_l4_ick2>;
46 clocks = <&security_l4_ick2>;
54 clocks = <&dpll4_m5x2_ck>;
63 clocks = <&l4_ick>;
71 clocks = <&core_96m_fck>;
79 clocks = <&l3_ick>;
87 clocks = <&security_l3_ick>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5433-clock.yaml16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
20 All available clocks are defined as preprocessor macros in
26 # CMU_TOP which generates clocks for
28 # clocks
30 # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
32 # CMU_MIF which generates clocks for DRAM Memory Controller domain
34 # CMU_PERIC which generates clocks for
37 # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
39 # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
42 # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
[all …]
H A Drenesas,cpg-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
17 the CPG Module Stop (MSTP) Clocks.
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
24 - const: renesas,r8a7778-cpg-clocks # R-Car M1
25 - const: renesas,r8a7779-cpg-clocks # R-Car H1
28 - renesas,r7s72100-cpg-clocks # RZ/A1H
29 - const: renesas,rz-cpg-clocks # RZ/A1
30 - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
[all …]
H A Dsamsung,exynos5260-clock.yaml16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
24 Phy clocks::
25 There are several clocks which are generated by specific PHYs. These clocks
27 These clocks are defined as fixed clocks in the driver with following names::
44 All available clocks are defined as preprocessor macros in
64 clocks:
91 clocks:
102 - clocks
111 clocks:
131 - clocks
[all …]
H A Drenesas,cpg-mstp-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
16 This device tree binding describes a single 32 gate clocks group per node.
17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
24 - renesas,r7s72100-mstp-clocks # RZ/A1
25 - renesas,r8a73a4-mstp-clocks # R-Mobile APE6
26 - renesas,r8a7740-mstp-clocks # R-Mobile A1
27 - renesas,r8a7778-mstp-clocks # R-Car M1
28 - renesas,r8a7779-mstp-clocks # R-Car H1
[all …]
H A Dsamsung,exynos7-clock.yaml16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
20 All available clocks are defined as preprocessor macros in
38 clocks:
65 clocks:
78 - clocks
87 clocks:
99 - clocks
108 clocks:
117 - clocks
126 clocks:
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap24xx-clocks.dtsi11 clocks = <&func_96m_ck>, <&mcbsp_clks>;
19 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
25 clocks = <&func_96m_ck>, <&mcbsp_clks>;
33 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
77 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
85 clocks = <&aplls_clkin_ck>;
93 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
102 clocks = <&osc_ck>;
124 clocks = <&sys_ck>, <&sys_ck>;
131 clocks = <&sys_ck>;
[all …]
H A Domap3xxx-clocks.dtsi17 …clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck…
24 clocks = <&osc_sys_ck>;
34 clocks = <&osc_sys_ck>;
42 clocks = <&dpll3_ck>;
50 clocks = <&dpll3_m2_ck>;
58 clocks = <&dpll4_ck>;
66 clocks = <&dpll3_m2x2_ck>;
74 clocks = <&sys_ck>;
92 clocks = <&core_96m_fck>, <&mcbsp_clks>;
100 clocks = <&per_96m_fck>, <&mcbsp_clks>;
[all …]
H A Domap2430-clocks.dtsi12 clocks = <&func_96m_ck>, <&mcbsp_clks>;
19 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
25 clocks = <&func_96m_ck>, <&mcbsp_clks>;
33 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
39 clocks = <&func_96m_ck>, <&mcbsp_clks>;
47 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
55 clocks = <&dsp_fck>;
63 clocks = <&dsp_fck>;
73 clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
79 clocks = <&core_ck>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dst,stih4xx.txt15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: names of the clocks listed in clocks property in the same
33 - clocks: from common clock binding: handle hardware IP needed clocks, the
34 number of clocks may depend of the SoC type.
35 See ../clocks/clock-bindings.txt for details.
36 - clock-names: names of the clocks listed in clocks property in the same
66 - clocks: from common clock binding: handle hardware IP needed clocks, the
67 number of clocks may depend of the SoC type.
[all …]
/openbmc/linux/drivers/clk/bcm/
H A Dclk-bcm281xx.c19 .clocks = CLOCKS("ref_crystal"),
35 .clocks = CLOCKS("bbl_32k",
44 .clocks = CLOCKS("ref_crystal",
53 .clocks = CLOCKS("var_312m",
77 .clocks = CLOCKS("ref_crystal",
96 .clocks = CLOCKS("ref_crystal",
108 .clocks = CLOCKS("ref_crystal",
120 .clocks = CLOCKS("ref_crystal",
132 .clocks = CLOCKS("ref_crystal",
144 .clocks = CLOCKS("ref_crystal",
[all …]
H A Dclk-bcm21664.c17 .clocks = CLOCKS("ref_crystal"),
35 .clocks = CLOCKS("bbl_32k",
59 .clocks = CLOCKS("ref_crystal",
71 .clocks = CLOCKS("ref_crystal",
83 .clocks = CLOCKS("ref_crystal",
95 .clocks = CLOCKS("ref_crystal",
106 .clocks = CLOCKS("ref_32k"), /* Verify */
111 .clocks = CLOCKS("ref_32k"), /* Verify */
116 .clocks = CLOCKS("ref_32k"), /* Verify */
121 .clocks = CLOCKS("ref_32k"), /* Verify */
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi40 clocks = <&timclk>, <&pclk>;
49 clocks = <&timclk>, <&pclk>;
64 clocks = <&pclk>;
78 clocks = <&pclk>;
92 clocks = <&pclk>;
107 clocks = <&pclk>;
215 clocks = <&mxtal>;
223 clocks = <&mxtal>;
230 clocks = <&pll1>;
238 clocks = <&hclk>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-dma.dtsi30 clocks = <&spi0_lpcg IMX_LPCG_CLK_0>,
33 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
46 clocks = <&spi1_lpcg IMX_LPCG_CLK_0>,
49 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
62 clocks = <&spi2_lpcg IMX_LPCG_CLK_0>,
65 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
78 clocks = <&spi3_lpcg IMX_LPCG_CLK_0>,
81 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
90 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
93 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
[all …]

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