| /openbmc/linux/arch/alpha/kernel/ |
| H A D | sys_marvel.c | 96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
98 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; in io7_get_irq_ctl()
196 val = io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
200 io7->csrs->PO7_LSI_CTL[which].csr = val; in io7_redirect_one_lsi()
202 io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
213 val = io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
217 io7->csrs->PO7_MSI_CTL[which].csr = val; in io7_redirect_one_msi()
219 io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
228 io7->csrs->PO7_LSI_CTL[which].csr = ((unsigned long)where << 14); in init_one_io7_lsi()
230 io7->csrs->PO7_LSI_CTL[which].csr; in init_one_io7_lsi()
[all …]
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| H A D | core_marvel.c | 174 io7_ioport_csrs *csrs; in io7_clear_errors() local
182 csrs = IO7_CSRS_KERN(io7->pe, port); in io7_clear_errors()
184 csrs->POx_ERR_SUM.csr = -1UL; in io7_clear_errors()
185 csrs->POx_TLB_ERR.csr = -1UL; in io7_clear_errors()
186 csrs->POx_SPL_COMPLT.csr = -1UL; in io7_clear_errors()
187 csrs->POx_TRANS_SUM.csr = -1UL; in io7_clear_errors()
211 io7_ioport_csrs *csrs = IO7_CSRS_KERN(io7->pe, port); in io7_init_hose() local
227 io7_port->csrs = csrs; in io7_init_hose()
268 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr; in io7_init_hose()
269 io7_port->saved_wmask[i] = csrs->POx_WMASK[i].csr; in io7_init_hose()
[all …]
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| H A D | err_marvel.c | 818 err_sum |= io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
822 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr; in marvel_find_io7_with_error()
843 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr; in marvel_find_io7_with_error()
844 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr; in marvel_find_io7_with_error()
845 io->io7_uph = io7->csrs->IO7_UPH.csr; in marvel_find_io7_with_error()
846 io->hpi_ctl = io7->csrs->HPI_CTL.csr; in marvel_find_io7_with_error()
847 io->crd_ctl = io7->csrs->CRD_CTL.csr; in marvel_find_io7_with_error()
848 io->hei_ctl = io7->csrs->HEI_CTL.csr; in marvel_find_io7_with_error()
849 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
850 io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr; in marvel_find_io7_with_error()
[all …]
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| /openbmc/qemu/target/loongarch/ |
| H A D | cpu-csr.h | 3 * QEMU LoongArch CSRs
15 /* Basic CSRs */
53 /* TLB related CSRs */
113 /* Config CSRs */
135 /* Timer CSRs */
149 /* LLBCTL CSRs */
160 /* TLB Refill CSRs */
178 /* Machine Error CSRs */
189 /* Direct map windows CSRs*/
200 /* Debug CSRs */
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| /openbmc/qemu/target/riscv/ |
| H A D | cpu_bits.h | 52 /* User Floating-Point CSRs */
57 /* User Vector CSRs */
184 /* Machine-Level High-Half CSRs (AIA) */
197 /* Supervisor Configuration CSRs */
200 /* Supervisor state CSRs */
213 /* Sstc supervisor CSRs */
229 /* Supervisor-Level High-Half CSRs (AIA) */
233 /* Hpervisor CSRs */
249 /* Hypervisor Configuration CSRs */
253 /* Hypervisor state CSRs */
[all …]
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| H A D | cpu.h | 251 /* CSRs for execution environment configuration */
312 /* AIA CSRs */
318 /* Hypervisor CSRs */
342 /* Upper 64-bits of 128-bit CSRs */
346 /* Virtual CSRs */
359 /* AIA VS-mode CSRs */
365 /* HS Backup CSRs */
410 /* Sstc CSRs */
455 * CSRs for PointerMasking extension
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| /openbmc/linux/arch/alpha/include/asm/ |
| H A D | core_t2.h | 68 /* The CSRs below are T3/T4 only */
95 /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
99 * | CPU 0 CSRs |
101 * | CPU 1 CSRs |
103 * | CPU 2 CSRs |
105 * | CPU 3 CSRs |
111 * | Mem 0 CSRs |
113 * | Mem 1 CSRs |
115 * | Mem 2 CSRs |
117 * | Mem 3 CSRs |
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | riscv,cpu-intc.txt | 4 RISC-V cores include Control Status Registers (CSRs) which are local to each
6 Some of these CSRs are used to control local interrupts connected to the core.
40 definition of the hart whose CSRs control these local interrupts.
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie-ep.yaml | 47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
73 set of viewport CSRs mapped into the PL space. Note iATU is
79 CSRs mapped in a non-standard base address. The registers offset
86 PCS and PHY CSRs accessible over a dedicated memory mapped
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| H A D | snps,dw-pcie.yaml | 56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
82 set of viewport CSRs mapped into the PL space. Note iATU is
88 CSRs mapped in a non-standard base address. The registers offset
95 PCS and PHY CSRs accessible over a dedicated memory mapped
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| /openbmc/linux/include/linux/ |
| H A D | litex.h | 4 * helper functions for accessing CSRs.
34 * means that only larger-than-32-bit CSRs will be split across multiple
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| /openbmc/linux/arch/riscv/kernel/ |
| H A D | suspend.c | 55 /* Save additional CSRs*/ in cpu_suspend()
83 /* Restore additional CSRs */ in cpu_suspend()
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| H A D | suspend_entry.S | 45 /* Save CSRs */
87 /* Restore CSRs */
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| H A D | fpu.S | 26 csrs CSR_STATUS, t1
70 csrs CSR_STATUS, t1
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| H A D | head.S | 400 csrs CSR_STATUS, t1
450 csrs CSR_STATUS, t1
451 csrs CSR_VCSR, x0
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| /openbmc/linux/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| H A D | nfp_arm.h | 145 /* Gasket CSRs */
151 /* BAR CSRs
210 /* MP Core CSRs */
213 /* PL320 CSRs */
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| /openbmc/linux/drivers/pci/controller/dwc/ |
| H A D | pcie-designware.h | 131 * iATU inbound and outbound windows CSRs. Before the IP-core v4.80a each
132 * iATU region CSRs had been indirectly accessible by means of the dedicated
133 * viewport selector. The iATU/eDMA CSRs space was re-designed in DWC PCIe
135 * iATU/eDMA CSRs space.
173 * eDMA CSRs. DW PCIe IP-core v4.70a and older had the eDMA registers accessible
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| /openbmc/linux/arch/riscv/kvm/ |
| H A D | vcpu_switch.S | 242 csrs CSR_SSTATUS, t1
285 csrs CSR_SSTATUS, t1
329 csrs CSR_SSTATUS, t1
372 csrs CSR_SSTATUS, t1
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| H A D | vcpu.c | 86 /* Reset the guest CSRs for hotplug usecase */ in kvm_riscv_reset_vcpu()
121 /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */ in kvm_arch_vcpu_create()
345 /* Read current HVIP and VSIE CSRs */ in kvm_riscv_vcpu_sync_interrupts()
365 /* Sync-up timer CSRs */ in kvm_riscv_vcpu_sync_interrupts()
761 * local_irq_enable() which can potentially change CSRs. in kvm_arch_vcpu_ioctl_run()
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| /openbmc/linux/drivers/infiniband/hw/hfi1/ |
| H A D | chip.h | 580 * per-context or per-SDMA CSRs that are not mappable to user-space.
586 /* kernel per-context CSRs are separated by 0x100 */ in read_kctxt_csr()
593 /* kernel per-context CSRs are separated by 0x100 */ in write_kctxt_csr()
614 * per-context CSRs that are mappable to user space. All these CSRs
616 * different processes without exposing other contexts' CSRs
621 /* user per-context CSRs are separated by 0x1000 */ in read_uctxt_csr()
628 /* user per-context CSRs are separated by 0x1000 */ in write_uctxt_csr()
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| /openbmc/linux/arch/riscv/include/asm/ |
| H A D | csr.h | 296 /* Supervisor-Level High-Half CSRs (AIA) */
343 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
383 /* Machine-Level High-Half CSRs (AIA) */
494 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
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| H A D | cpufeature.h | 14 * from the corresponding CSRs.
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| /openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/ |
| H A D | lmac_common.h | 57 /* Features like RXSTAT, TXSTAT, DMAC FILTER csrs differs by fixed
158 /* Lock to serialize read/write of global csrs like
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| /openbmc/linux/drivers/tty/serial/ |
| H A D | liteuart.c | 23 * CSRs definitions (base address offsets + width)
29 * generic way of indexing the LiteX CSRs.
31 * For more details on how CSRs are defined and handled in LiteX, see comments
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| /openbmc/linux/drivers/net/ethernet/sfc/falcon/ |
| H A D | io.h | 22 * Many CSRs are very wide and cannot be read or written atomically.
30 * Writes to different CSRs and 64-bit SRAM words must be serialised,
34 * We also serialise reads from 128-bit CSRs and SRAM with the same
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