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Searched full:clkdiv (Results 1 – 25 of 93) sorted by relevance

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/openbmc/linux/drivers/clk/qcom/
H A Dclk-spmi-pmic-div.c24 struct clkdiv { struct
33 static inline struct clkdiv *to_clkdiv(struct clk_hw *hw) in to_clkdiv() argument
35 return container_of(hw, struct clkdiv, hw); in to_clkdiv()
51 static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv) in is_spmi_pmic_clkdiv_enabled() argument
55 regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); in is_spmi_pmic_clkdiv_enabled()
61 __spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable, in __spmi_pmic_clkdiv_set_enable_state() argument
65 unsigned int ns = clkdiv->cxo_period_ns; in __spmi_pmic_clkdiv_set_enable_state()
68 ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL, in __spmi_pmic_clkdiv_set_enable_state()
81 static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable) in spmi_pmic_clkdiv_set_enable_state() argument
85 regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor); in spmi_pmic_clkdiv_set_enable_state()
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-cavium.h46 uint64_t clkdiv:13; member
78 uint64_t clkdiv:13;
85 uint64_t clkdiv:13; member
111 uint64_t clkdiv:13;
118 uint64_t clkdiv:13; member
142 uint64_t clkdiv:13;
150 uint64_t clkdiv:13; member
180 uint64_t clkdiv:13;
187 uint64_t clkdiv:13; member
217 uint64_t clkdiv:13;
H A Dspi-cavium.c36 unsigned int clkdiv; in octeon_spi_do_transfer() local
48 clkdiv = p->sys_freq / (2 * xfer->speed_hz); in octeon_spi_do_transfer()
52 mpi_cfg.s.clkdiv = clkdiv; in octeon_spi_do_transfer()
/openbmc/u-boot/drivers/mmc/
H A Dgen_atmel_mci.c105 u32 clkdiv = 255; local
114 clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
115 if (clkdiv > 511)
116 clkdiv = 511;
118 clkodd = clkdiv & 1;
119 clkdiv >>= 1;
122 bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
124 /* find clkdiv yielding a rate <= than requested */
125 for (clkdiv = 0; clkdiv < 255; clkdiv++) {
126 if ((bus_hz / (clkdiv + 1) / 2) <= hz)
[all …]
H A Darm_pl180_mmci.c291 u32 clkdiv = 0; in host_set_ios() local
295 clkdiv = 0; in host_set_ios()
298 clkdiv = (host->clock_in / dev->clock) - 2; in host_set_ios()
301 tmp_clock = host->clock_in / (clkdiv + 2); in host_set_ios()
303 clkdiv++; in host_set_ios()
304 tmp_clock = host->clock_in / (clkdiv + 2); in host_set_ios()
307 if (clkdiv > SDI_CLKCR_CLKDIV_MASK) in host_set_ios()
308 clkdiv = SDI_CLKCR_CLKDIV_MASK; in host_set_ios()
310 tmp_clock = host->clock_in / (clkdiv + 2); in host_set_ios()
313 sdi_clkcr |= clkdiv; in host_set_ios()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,spmi-clkdiv.yaml4 $id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml#
20 const: qcom,spmi-clkdiv
38 description: Number of CLKDIV peripherals.
57 compatible = "qcom,spmi-clkdiv";
H A Drenesas,emev2-smu.yaml49 const: renesas,emev2-smu-clkdiv
129 compatible = "renesas,emev2-smu-clkdiv";
H A Dbaikal,bt1-ccu-div.yaml58 CLKDIV--|--| | | |-|->CLKLOUT
68 accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
72 figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
/openbmc/linux/drivers/hwtracing/intel_th/
H A Dpti.c27 unsigned int clkdiv; member
113 return scnprintf(buf, PAGE_SIZE, "%d\n", 1u << pti->clkdiv); in clock_divider_show()
131 pti->clkdiv = val; in clock_divider_store()
159 ctl |= pti->clkdiv << __ffs(PTI_CLKDIV); in intel_th_pti_activate()
183 pti->clkdiv = (ctl & PTI_CLKDIV) >> __ffs(PTI_CLKDIV); in read_hw_config()
188 if (!pti->clkdiv) in read_hw_config()
189 pti->clkdiv = 1; in read_hw_config()
/openbmc/u-boot/board/sbc8548/
H A Dsbc8548.c60 uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR; in local_bus_init() local
66 clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus; in local_bus_init()
68 debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz); in local_bus_init()
71 if (clkdiv == 16) { in local_bus_init()
73 } else if (clkdiv == 8) { in local_bus_init()
75 } else if (clkdiv == 4) { in local_bus_init()
/openbmc/linux/sound/soc/intel/skylake/
H A Dskl-nhlt.c211 u32 clkdiv, div_ratio; in skl_get_mclk() local
222 clkdiv = i2s_config->mclk.mdivr & in skl_get_mclk()
227 clkdiv = i2s_config_ext->mclk.mdivr[0] & in skl_get_mclk()
234 if (clkdiv != SKL_MCLK_DIV_RATIO_MASK) in skl_get_mclk()
235 /* Divider is 2 + clkdiv */ in skl_get_mclk()
236 div_ratio = clkdiv + 2; in skl_get_mclk()
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Demev2.dtsi72 compatible = "renesas,emev2-smu-clkdiv";
84 compatible = "renesas,emev2-smu-clkdiv";
103 compatible = "renesas,emev2-smu-clkdiv";
109 compatible = "renesas,emev2-smu-clkdiv";
115 compatible = "renesas,emev2-smu-clkdiv";
121 compatible = "renesas,emev2-smu-clkdiv";
/openbmc/linux/drivers/w1/masters/
H A Dmxc_w1.c95 unsigned int clkdiv; in mxc_w1_probe() local
116 clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000); in mxc_w1_probe()
117 clkrate /= clkdiv; in mxc_w1_probe()
132 writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER); in mxc_w1_probe()
/openbmc/linux/drivers/pwm/
H A Dpwm-tiehrpwm.c153 unsigned int clkdiv, hspclkdiv; in set_prescale_div() local
155 for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { in set_prescale_div()
161 * CLKDIVIDER = (1), if clkdiv == 0 *OR* in set_prescale_div()
162 * (2 * clkdiv), if clkdiv != 0 in set_prescale_div()
168 *prescale_div = (1 << clkdiv) * in set_prescale_div()
171 *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | in set_prescale_div()
H A Dpwm-mediatek.c125 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, in pwm_mediatek_config() local
146 clkdiv++; in pwm_mediatek_config()
151 if (clkdiv > PWM_CLK_DIV_MAX) { in pwm_mediatek_config()
167 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); in pwm_mediatek_config()
/openbmc/linux/sound/soc/adi/
H A Daxi-spdif.c80 unsigned int clkdiv, stat; in axi_spdif_hw_params() local
97 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), in axi_spdif_hw_params()
99 clkdiv <<= AXI_SPDIF_CTRL_CLKDIV_OFFSET; in axi_spdif_hw_params()
103 AXI_SPDIF_CTRL_CLKDIV_MASK, clkdiv); in axi_spdif_hw_params()
/openbmc/u-boot/drivers/w1/
H A Dmxc_w1.c184 unsigned int clkdiv; in mxc_w1_probe() local
192 clkdiv = clkrate / 1000000; in mxc_w1_probe()
193 clkrate /= clkdiv; in mxc_w1_probe()
199 writew(clkdiv - 1, &pdata->regs->time_divider); in mxc_w1_probe()
/openbmc/linux/sound/soc/codecs/
H A Dadau1701.c300 static int adau1701_reset(struct snd_soc_component *component, unsigned int clkdiv, in adau1701_reset() argument
309 if (clkdiv != ADAU1707_CLKDIV_UNSET && adau1701->gpio_pll_mode) { in adau1701_reset()
310 switch (clkdiv) { in adau1701_reset()
334 adau1701->pll_clkdiv = clkdiv; in adau1701_reset()
349 if (clkdiv != ADAU1707_CLKDIV_UNSET) { in adau1701_reset()
441 unsigned int clkdiv = adau1701->sysclk / params_rate(params); in adau1701_hw_params() local
450 if (clkdiv != adau1701->pll_clkdiv) { in adau1701_hw_params()
451 ret = adau1701_reset(component, clkdiv, params_rate(params)); in adau1701_hw_params()
824 of_property_read_u32(dev->of_node, "adi,pll-clkdiv", in adau1701_i2c_probe()
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c1500 static int set_clkdiv(unsigned int clkdiv, u32 address) in set_clkdiv() argument
1505 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK); in set_clkdiv()
1509 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n", in set_clkdiv()
1510 clkdiv, address, readl(address)); in set_clkdiv()
1516 u32 clksrc, u32 clkdiv) in stm32mp1_mco_csg() argument
1533 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); in stm32mp1_mco_csg()
1579 unsigned int clkdiv[CLKDIV_NB]; in stm32mp1_clktree() local
1594 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB); in stm32mp1_clktree()
1596 debug("field st,clkdiv invalid: error %d\n", ret); in stm32mp1_clktree()
1617 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); in stm32mp1_clktree()
[all …]
/openbmc/u-boot/board/freescale/mpc8548cds/
H A Dmpc8548cds.c69 uint clkdiv; in local_bus_init() local
73 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; in local_bus_init()
76 if (clkdiv == 16) { in local_bus_init()
78 } else if (clkdiv == 8) { in local_bus_init()
80 } else if (clkdiv == 4) { in local_bus_init()
/openbmc/linux/drivers/iio/adc/
H A Dlpc18xx_adc.c133 unsigned int clkdiv; in lpc18xx_adc_probe() local
176 clkdiv = DIV_ROUND_UP(rate, LPC18XX_ADC_CLK_TARGET); in lpc18xx_adc_probe()
178 adc->cr_reg = (clkdiv << LPC18XX_ADC_CR_CLKDIV_SHIFT) | in lpc18xx_adc_probe()
/openbmc/u-boot/board/freescale/mpc8568mds/
H A Dmpc8568mds.c132 uint clkdiv; in local_bus_init() local
136 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; in local_bus_init()
139 if (clkdiv == 16) { in local_bus_init()
141 } else if (clkdiv == 8) { in local_bus_init()
143 } else if (clkdiv == 4) { in local_bus_init()
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_adc-test.c170 uint32_t clkdiv) in adc_calculate_steps() argument
172 return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale; in adc_calculate_steps()
176 uint32_t clkdiv) in adc_wait_conv_finished() argument
185 clkdiv)); in adc_wait_conv_finished()
188 qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv)); in adc_wait_conv_finished()
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dexynos7_drm_decon.c144 u32 clkdiv; in decon_calc_clkdiv() local
147 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); in decon_calc_clkdiv()
149 return (clkdiv < 0x100) ? clkdiv : 0xff; in decon_calc_clkdiv()
156 u32 val, clkdiv; in decon_commit() local
205 clkdiv = decon_calc_clkdiv(ctx, mode); in decon_commit()
206 if (clkdiv > 1) { in decon_commit()
207 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); in decon_commit()
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dlpc32xx_nand_mlc.c89 #define clkdiv(v, w, o) (((1+(clk/v)) & w) << o) macro
142 clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | in lpc32xx_nand_init()
143 clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | in lpc32xx_nand_init()
144 clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | in lpc32xx_nand_init()
145 clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | in lpc32xx_nand_init()
146 clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | in lpc32xx_nand_init()
147 clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | in lpc32xx_nand_init()
148 clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), in lpc32xx_nand_init()

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