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/openbmc/linux/drivers/crypto/inside-secure/
H A Dsafexcel_ring.c14 struct safexcel_desc_ring *cdr, in safexcel_init_ring_descriptors() argument
22 cdr->offset = priv->config.cd_offset; in safexcel_init_ring_descriptors()
23 cdr->base = dmam_alloc_coherent(priv->dev, in safexcel_init_ring_descriptors()
24 cdr->offset * EIP197_DEFAULT_RING_SIZE, in safexcel_init_ring_descriptors()
25 &cdr->base_dma, GFP_KERNEL); in safexcel_init_ring_descriptors()
26 if (!cdr->base) in safexcel_init_ring_descriptors()
28 cdr->write = cdr->base; in safexcel_init_ring_descriptors()
29 cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1); in safexcel_init_ring_descriptors()
30 cdr->read = cdr->base; in safexcel_init_ring_descriptors()
33 cdr->shoffset = priv->config.cdsh_offset; in safexcel_init_ring_descriptors()
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/meta-python/recipes-dbs/mongodb/mongodb/
H A D1296.patch7 parse(ConstDataRange cdr, size_t* outLength);
8 to parse(ConstDataRange cdr, uint64_t* outLength);
32 - static StatusWith<DERToken> parse(ConstDataRange cdr, size_t* outLength);
33 + static StatusWith<DERToken> parse(ConstDataRange cdr, uint64_t* outLength);
50 -StatusWith<DERToken> DERToken::parse(ConstDataRange cdr, size_t* outLength) {
51 +StatusWith<DERToken> DERToken::parse(ConstDataRange cdr, uint64_t* outLength) {
/openbmc/linux/drivers/net/can/sja1000/
H A Dsja1000_isa.c35 static unsigned char cdr[MAXDEV] = {[0 ... (MAXDEV - 1)] = 0xff}; variable
56 module_param_array(cdr, byte, NULL, 0444);
57 MODULE_PARM_DESC(cdr, "Clock divider register "
190 if (cdr[idx] != 0xff) in sja1000_isa_probe()
191 priv->cdr = cdr[idx]; in sja1000_isa_probe()
192 else if (cdr[0] != 0xff) in sja1000_isa_probe()
193 priv->cdr = cdr[0]; in sja1000_isa_probe()
195 priv->cdr = CDR_DEFAULT; in sja1000_isa_probe()
H A Dsja1000_platform.c118 priv->cdr = pdata->cdr; in sp_populate()
186 priv->cdr |= divider / 2 - 1; in sp_populate_of()
188 priv->cdr |= CDR_CLKOUT_MASK; in sp_populate_of()
190 priv->cdr |= CDR_CLK_OFF; /* default */ in sp_populate_of()
194 priv->cdr |= CDR_CBP; /* default */ in sp_populate_of()
H A Dems_pcmcia.c48 * In the CDR register, you should set CBP to 1.
218 priv->cdr = EMS_PCMCIA_CDR; in ems_pcmcia_add_card()
H A Dplx_pci.c79 * In the CDR register, you should set CBP to 1.
157 u8 cdr; /* clock divider register */ member
692 priv->cdr = ci->cdr; in plx_pci_add_card()
H A Dkvaser_pci.c63 * In the CDR register, you should set CBP to 1.
249 priv->cdr = KVASER_PCI_CDR; in kvaser_pci_add_chan()
/openbmc/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-errata.c43 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
45 * CDR for the specified QLM.
47 * @qlm: QLM to disable 2nd order CDR for.
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Damd-xgbe.txt46 - amd,serdes-cdr-rate: CDR rate speed selection
71 amd,serdes-cdr-rate = <2>, <2>, <7>;
H A Dcortina.txt7 devices, equipped with clock and data recovery (CDR) circuits. These
/openbmc/qemu/hw/gpio/
H A Dzaurus.c45 uint16_t cdr; member
87 return s->cdr; in scoop_read()
125 s->cdr = value; in scoop_write()
236 VMSTATE_UINT16(cdr, ScoopInfo),
/openbmc/entity-manager/configurations/
H A Dcompuware_cdr_9011_3m1_psu.json115 "Name": "COMPUWARE CDR 9011 3M1 PSU$address % 4 + 1",
116 …project.FruDevice({'PRODUCT_MANUFACTURER': 'COMPUWARE', 'PRODUCT_PRODUCT_NAME': 'CDR-9011-3M1*'})",
/openbmc/qemu/tests/qtest/
H A Dcdrom-test.c142 "-device virtio-scsi -device scsi-cd,drive=cdr " in add_x86_tests()
143 "-blockdev file,node-name=cdr,filename=", in add_x86_tests()
208 "-device virtio-scsi -device scsi-cd,drive=cdr " in add_s390x_tests()
209 "-blockdev file,node-name=cdr,filename=", test_cdboot); in add_s390x_tests()
/openbmc/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c58 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
100 temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF)); in clock_limp()
103 out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); in clock_limp()
/openbmc/linux/drivers/infiniband/hw/hfi1/
H A Dplatform.c295 /* RX CDR present, bypass supported */ in apply_rx_cdr()
299 /* Power class <= 3, ignore config & turn RX CDR on */ in apply_rx_cdr()
321 /* Expand cdr setting to all 4 lanes */ in apply_rx_cdr()
329 /* Preserve current TX CDR status */ in apply_rx_cdr()
346 /* TX CDR present, bypass supported */ in apply_tx_cdr()
350 /* Power class <= 3, ignore config & turn TX CDR on */ in apply_tx_cdr()
373 /* Expand cdr setting to all 4 lanes */ in apply_tx_cdr()
380 /* Preserve current/determined RX CDR status */ in apply_tx_cdr()
/openbmc/u-boot/arch/arm/dts/
H A Dexynos5420-peach-pit.dts113 * [3:2] CDR tune wait cycle before
126 * 2.7G CDR settings
127 * NOF=40LSB for HBR CDR setting
133 * 1.62G CDR settings
H A Dexynos5250-spring.dts600 * RPHY Setting: [3:2] CDR tune wait cycle before
610 /* 2.7G CDR settings */
611 0x04 0x7d 0x07 /* NOF=40LSB for HBR CDR setting */
615 * 1.62G CDR settings:
/openbmc/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-xgbe-b.dtsi49 amd,serdes-cdr-rate = <2>, <2>, <7>;
75 amd,serdes-cdr-rate = <2>, <2>, <7>;
/openbmc/u-boot/include/
H A Dsja1000.h27 u8 cdr; member
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c110 * [3:2] CDR tune wait cycle before measure for fine tune in ps8622_send_config()
127 /* 2.7G CDR settings: NOF=40LSB for HBR CDR setting */ in ps8622_send_config()
142 /* 1.62G CDR settings: [5:2]NOF=64LSB [1:0]DCO scale is 2/5 */ in ps8622_send_config()
/openbmc/linux/include/linux/can/platform/
H A Dsja1000.h33 u8 cdr; /* clock divider register */ member
/openbmc/u-boot/drivers/misc/
H A Dmpc83xx_serdes.h115 * KFRA = 'Kfr' gain selection in the CDR for lane A
116 * KFRE = 'Kfr' gain selection in the CDR for lane E
/openbmc/linux/drivers/net/phy/
H A Dcortina.c97 MODULE_DESCRIPTION("Cortina EDC CDR 10G Ethernet PHY driver");
/openbmc/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c301 pr_debug("XGBE: CDR centered, DLPF: %4d,%d,%d.\n", in netcp_xgbe_serdes_reset_cdr()
341 /* if no lock, then reset CDR */ in netcp_xgbe_check_link_status()
361 /* Lost the block lock, reset CDR if it is in netcp_xgbe_check_link_status()
/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Dti,ds90ub960.yaml89 ti,cdr-mode:
95 FPD-Link CDR Mode. This should reflect the hardware and the

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