| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-imx25.c | 42 #define ccm(x) (ccm_base + (x)) macro
82 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
83 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); in __mx25_clocks_init()
85 …clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)… in __mx25_clocks_init()
86 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); in __mx25_clocks_init()
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
88 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); in __mx25_clocks_init()
90 …clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)… in __mx25_clocks_init()
91 …clk[per1_sel] = imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)… in __mx25_clocks_init()
92 …clk[per2_sel] = imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)… in __mx25_clocks_init()
[all …]
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| H A D | Kconfig | 67 tristate "IMX8MM CCM Clock Driver"
71 Build the driver for i.MX8MM CCM Clock Driver
74 tristate "IMX8MN CCM Clock Driver"
78 Build the driver for i.MX8MN CCM Clock Driver
81 tristate "IMX8MP CCM Clock Driver"
85 Build the driver for i.MX8MP CCM Clock Driver
88 tristate "IMX8MQ CCM Clock Driver"
92 Build the driver for i.MX8MQ CCM Clock Driver
104 tristate "IMX8ULP CCM Clock Driver"
108 Build the driver for i.MX8ULP CCM Clock Driver
[all …]
|
| H A D | clk-imx1.c | 28 static void __iomem *ccm __initdata;
29 #define CCM_CSCR (ccm + 0x0000)
30 #define CCM_MPCTL0 (ccm + 0x0004)
31 #define CCM_SPCTL0 (ccm + 0x000c)
32 #define CCM_PCDR (ccm + 0x0020)
33 #define SCM_GCCR (ccm + 0x0810)
37 ccm = of_iomap(np, 0); in mx1_clocks_init_dt()
38 BUG_ON(!ccm); in mx1_clocks_init_dt()
72 CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);
|
| /openbmc/linux/drivers/net/ethernet/netronome/nfp/ |
| H A D | ccm.c | 6 #include "ccm.h"
14 static bool nfp_ccm_all_tags_busy(struct nfp_ccm *ccm) in nfp_ccm_all_tags_busy() argument
18 used_tags = ccm->tag_alloc_next - ccm->tag_alloc_last; in nfp_ccm_all_tags_busy()
23 static int nfp_ccm_alloc_tag(struct nfp_ccm *ccm) in nfp_ccm_alloc_tag() argument
25 /* CCM is for FW communication which is request-reply. To make sure in nfp_ccm_alloc_tag()
29 if (unlikely(nfp_ccm_all_tags_busy(ccm))) { in nfp_ccm_alloc_tag()
30 ccm_warn(ccm->app, "all FW request contexts busy!\n"); in nfp_ccm_alloc_tag()
34 WARN_ON(__test_and_set_bit(ccm->tag_alloc_next, ccm->tag_allocator)); in nfp_ccm_alloc_tag()
35 return ccm->tag_alloc_next++; in nfp_ccm_alloc_tag()
38 static void nfp_ccm_free_tag(struct nfp_ccm *ccm, u16 tag) in nfp_ccm_free_tag() argument
[all …]
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | clock_sun9i.c | 23 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
38 C0_CFG_APB0_CLK_DIV_RATIO(2), &ccm->c0_cfg); in clock_init_safe()
42 &ccm->ahb0_cfg); in clock_init_safe()
45 &ccm->ahb1_cfg); in clock_init_safe()
48 &ccm->ahb2_cfg); in clock_init_safe()
51 &ccm->apb0_cfg); in clock_init_safe()
55 &ccm->gtbus_cfg); in clock_init_safe()
58 &ccm->cci400_cfg); in clock_init_safe()
61 setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24)); in clock_init_safe()
62 setbits_le32(&ccm->apb1_gate, (1 << 24)); in clock_init_safe()
[all …]
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| H A D | clock_sun6i.c | 21 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
39 writel(GENMASK(12, 0), &ccm->pll_lock_ctrl); in clock_init_safe()
44 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
45 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) in clock_init_safe()
48 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); in clock_init_safe()
50 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); in clock_init_safe()
52 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); in clock_init_safe()
55 setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT); in clock_init_safe()
56 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
57 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
[all …]
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| H A D | clock_sun8i_a83t.c | 21 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
26 writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg); in clock_init_safe()
27 writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); in clock_init_safe()
28 while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {} in clock_init_safe()
31 writel(0x0, &ccm->cci400_cfg); in clock_init_safe()
33 writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg); in clock_init_safe()
37 clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK, in clock_init_safe()
39 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
40 while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {} in clock_init_safe()
42 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); in clock_init_safe()
[all …]
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| H A D | clock_sun50i_h6.c | 9 struct sunxi_ccm_reg *const ccm = in clock_init_safe() local
13 writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
14 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK)) in clock_init_safe()
17 clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, in clock_init_safe()
20 writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg); in clock_init_safe()
21 writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg); in clock_init_safe()
22 writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg); in clock_init_safe()
28 writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg); in clock_init_safe()
34 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
41 &ccm->apb2_cfg); in clock_init_uart()
[all …]
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| H A D | clock_sun4i.c | 21 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
29 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
30 writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); in clock_init_safe()
36 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
38 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); in clock_init_safe()
40 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
42 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
43 setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); in clock_init_safe()
50 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
57 &ccm->apb1_clk_div_cfg); in clock_init_uart()
[all …]
|
| /openbmc/linux/net/bridge/ |
| H A D | br_private_cfm.h | 40 /* Expected received CCM PDU MAID. */
43 /* Expected received CCM PDU interval. */
44 /* Transmitting CCM PDU interval when CCM tx is enabled. */
47 bool enable; /* Enable/disable CCM PDU handling */
62 /* Transmitted CCM Remote Defect Indication status set.
63 * This RDI is inserted in transmitted CCM PDUs if CCM transmission is enabled.
72 /* The CCM will be transmitted for this period in seconds.
78 bool seq_no_update; /* Update Tx CCM sequence number */
100 /* This CCM related status is based on the latest received CCM PDU. */
104 /* CCM has not been received for 3.25 intervals */
[all …]
|
| /openbmc/qemu/hw/misc/ |
| H A D | imx6_ccm.c | 10 * the CCM.
239 VMSTATE_UINT32_ARRAY(ccm, IMX6CCMState, CCM_MAX),
288 switch (EXTRACT(dev->ccm[CCM_CBCMR], PRE_PERIPH_CLK_SEL)) { in imx6_analog_get_periph_clk()
316 / (1 + EXTRACT(dev->ccm[CCM_CBCDR], AHB_PODF)); in imx6_ccm_get_ahb_clk()
328 / (1 + EXTRACT(dev->ccm[CCM_CBCDR], IPG_PODF)); in imx6_ccm_get_ipg_clk()
340 / (1 + EXTRACT(dev->ccm[CCM_CSCMR1], PERCLK_PODF)); in imx6_ccm_get_per_clk()
387 s->ccm[CCM_CCR] = 0x040116FF; in imx6_ccm_reset()
388 s->ccm[CCM_CCDR] = 0x00000000; in imx6_ccm_reset()
389 s->ccm[CCM_CSR] = 0x00000010; in imx6_ccm_reset()
390 s->ccm[CCM_CCSR] = 0x00000100; in imx6_ccm_reset()
[all …]
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| H A D | imx6ul_ccm.c | 10 * the CCM.
289 VMSTATE_UINT32_ARRAY(ccm, IMX6ULCCMState, CCM_MAX),
368 switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PERIPH_CLK2_SEL)) { in imx6ul_ccm_get_periph_clk2_sel_clk()
398 switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PRE_PERIPH_CLK_SEL)) { in imx6ul_ccm_get_periph_clk_sel_clk()
425 / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK2_PODF)); in imx6ul_ccm_get_periph_clk2_clk()
436 switch (FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK_SEL)) { in imx6ul_ccm_get_periph_sel_clk()
457 / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, AHB_PODF)); in imx6ul_ccm_get_ahb_clk()
469 / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, IPG_PODF)); in imx6ul_ccm_get_ipg_clk()
480 switch (FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_CLK_SEL)) { in imx6ul_ccm_get_per_sel_clk()
501 / (1 + FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_PODF)); in imx6ul_ccm_get_per_clk()
[all …]
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | data-fabric.json | 516 …n": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 0.",
524 …n": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 1.",
532 …n": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 2.",
540 …n": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 3.",
548 …n": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 4.",
556 …n": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 5.",
564 …n": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 6.",
572 …n": "Data beats (32 bytes) at interface 0 for local socket inbound data to CPU Moderator (CCM) 7.",
580 …n": "Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 0.",
588 …n": "Data beats (32 bytes) at interface 1 for local socket inbound data to CPU Moderator (CCM) 1.",
[all …]
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/mx25/ |
| H A D | generic.c | 54 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_mpllclk() local
57 return imx_decode_pll(readl(&ccm->mpctl), fref); in imx_get_mpllclk()
62 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_upllclk() local
65 return imx_decode_pll(readl(&ccm->upctl), fref); in imx_get_upllclk()
70 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_armclk() local
71 ulong cctl = readl(&ccm->cctl); in imx_get_armclk()
86 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_ahbclk() local
87 ulong cctl = readl(&ccm->cctl); in imx_get_ahbclk()
104 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_perclk() local
105 ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() : in imx_get_perclk()
[all …]
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| /openbmc/u-boot/arch/arm/cpu/arm1136/mx35/ |
| H A D | generic.c | 133 struct ccm_regs *ccm = in get_mcu_main_clk() local
135 arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); in get_mcu_main_clk()
136 fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK); in get_mcu_main_clk()
143 struct ccm_regs *ccm = in get_ipg_clk() local
145 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_clk()
153 struct ccm_regs *ccm = in get_ipg_per_clk() local
155 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_per_clk()
156 u32 pdr4 = readl(&ccm->pdr4); in get_ipg_per_clk()
174 struct ccm_regs *ccm = in imx_get_uartclk() local
176 u32 pdr4 = readl(&ccm->pdr4); in imx_get_uartclk()
[all …]
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| /openbmc/u-boot/board/aristainetos/ |
| H A D | aristainetos-v2.c | 406 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in enable_lvds() local
411 reg = readl(&ccm->analog_pll_video); in enable_lvds()
413 writel(reg, &ccm->analog_pll_video); in enable_lvds()
420 writel(reg, &ccm->analog_pll_video); in enable_lvds()
423 &ccm->analog_pll_video_num); in enable_lvds()
425 &ccm->analog_pll_video_denom); in enable_lvds()
428 writel(reg, &ccm->analog_pll_video); in enable_lvds()
431 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) in enable_lvds()
436 reg = readl(&ccm->analog_pll_video); in enable_lvds()
439 writel(reg, &ccm->analog_pll_video); in enable_lvds()
[all …]
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| /openbmc/u-boot/board/freescale/vf610twr/ |
| H A D | vf610twr.c | 270 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in clock_init() local
273 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
275 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
277 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
282 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
284 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
287 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
289 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
291 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
293 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
[all …]
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| /openbmc/u-boot/board/barco/platinum/ |
| H A D | platinum.h | 66 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
68 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
69 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
70 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
71 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
72 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ in ccgr_init()
73 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
74 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
|
| /openbmc/u-boot/board/toradex/colibri_vf/ |
| H A D | colibri_vf.c | 378 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in clock_init() local
382 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
385 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK); in clock_init()
387 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
389 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
393 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
395 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
398 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
400 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
402 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
[all …]
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| /openbmc/u-boot/arch/arm/cpu/armv7/vf610/ |
| H A D | generic.c | 26 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in enable_ocotp_clk() local
29 reg = readl(&ccm->ccgr6); in enable_ocotp_clk()
34 writel(reg, &ccm->ccgr6); in enable_ocotp_clk()
40 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_mcu_main_clk() local
45 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk()
49 ccm_cacrr = readl(&ccm->cacrr); in get_mcu_main_clk()
104 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_bus_clk() local
107 ccm_cacrr = readl(&ccm->cacrr); in get_bus_clk()
118 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_ipg_clk() local
121 ccm_cacrr = readl(&ccm->cacrr); in get_ipg_clk()
[all …]
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| /openbmc/u-boot/board/CarMediaLab/flea3/ |
| H A D | flea3.c | 134 struct ccm_regs *ccm = in board_early_init_f() local
142 writel(CCM_CCMR_CONFIG, &ccm->ccmr); in board_early_init_f()
144 writel(CCM_MPLL_532_HZ, &ccm->mpctl); in board_early_init_f()
145 writel(CCM_PPLL_300_HZ, &ccm->ppctl); in board_early_init_f()
148 writel(0x00001000, &ccm->pdr0); in board_early_init_f()
154 writel(readl(&ccm->cgr0) | in board_early_init_f()
158 &ccm->cgr0); in board_early_init_f()
160 writel(readl(&ccm->cgr1) | in board_early_init_f()
168 &ccm->cgr1); in board_early_init_f()
171 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); in board_early_init_f()
|
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | imx5-clock.yaml | 20 - fsl,imx53-ccm
21 - fsl,imx51-ccm
22 - fsl,imx50-ccm
28 description: CCM provides 2 interrupt requests, request 1 is to generate
32 - description: CCM interrupt request 1
33 - description: CCM interrupt request 2
52 compatible = "fsl,imx53-ccm";
|
| /openbmc/u-boot/board/ccv/xpress/ |
| H A D | spl.c | 81 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
83 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
84 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
85 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
86 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
87 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
88 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
89 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
90 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
|
| /openbmc/u-boot/arch/m68k/cpu/mcf5445x/ |
| H A D | speed.c | 31 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_enter_limp() local
45 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); in clock_enter_limp()
49 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
58 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_exit_limp() local
62 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
72 ccm_t *ccm = (ccm_t *)MMAP_CCM; in setup_5441x_clocks() local
76 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14; in setup_5441x_clocks()
104 setbits_be16(&ccm->misccr2, 0x02); in setup_5441x_clocks()
117 if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */ in setup_5441x_clocks()
131 ccm_t *ccm = (ccm_t *)MMAP_CCM; in setup_5445x_clocks() local
[all …]
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| /openbmc/u-boot/board/tbs/tbs2910/ |
| H A D | tbs2910.c | 304 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
312 reg = readl(&ccm->analog_pll_video); in setup_display()
314 writel(reg, &ccm->analog_pll_video); in setup_display()
320 writel(reg, &ccm->analog_pll_video); in setup_display()
322 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); in setup_display()
323 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); in setup_display()
326 writel(reg, &ccm->analog_pll_video); in setup_display()
329 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) in setup_display()
334 reg = readl(&ccm->analog_pll_video); in setup_display()
337 writel(reg, &ccm->analog_pll_video); in setup_display()
[all …]
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