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/openbmc/linux/crypto/
H A Drmd160.c51 u32 aa, bb, cc, dd, ee, aaa, bbb, ccc, ddd, eee; in rmd160_transform() local
63 ccc = state[2]; in rmd160_transform()
158 ROUND(aaa, bbb, ccc, ddd, eee, F5, KK1, in[5], 8); in rmd160_transform()
159 ROUND(eee, aaa, bbb, ccc, ddd, F5, KK1, in[14], 9); in rmd160_transform()
160 ROUND(ddd, eee, aaa, bbb, ccc, F5, KK1, in[7], 9); in rmd160_transform()
161 ROUND(ccc, ddd, eee, aaa, bbb, F5, KK1, in[0], 11); in rmd160_transform()
162 ROUND(bbb, ccc, ddd, eee, aaa, F5, KK1, in[9], 13); in rmd160_transform()
163 ROUND(aaa, bbb, ccc, ddd, eee, F5, KK1, in[2], 15); in rmd160_transform()
164 ROUND(eee, aaa, bbb, ccc, ddd, F5, KK1, in[11], 15); in rmd160_transform()
165 ROUND(ddd, eee, aaa, bbb, ccc, F5, KK1, in[4], 5); in rmd160_transform()
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/openbmc/linux/include/linux/i3c/
H A Dccc.h14 /* I3C CCC (Common Command Codes) related definitions */
56 * struct i3c_ccc_events - payload passed to ENEC/DISEC CCC
60 * Depending on the CCC command, the specific events coming from all devices
69 * struct i3c_ccc_mwl - payload passed to SETMWL/GETMWL CCC
81 * struct i3c_ccc_mrl - payload passed to SETMRL/GETMRL CCC
121 * struct i3c_ccc_defslvs - payload passed to DEFSLVS CCC
150 * struct i3c_ccc_enttm - payload passed to ENTTM CCC
154 * Information passed to the ENTTM CCC to instruct an I3C device to enter a
174 * struct i3c_ccc_getpid - payload passed to GETPID CCC
183 * struct i3c_ccc_getbcr - payload passed to GETBCR CCC
[all …]
H A Dmaster.h15 #include <linux/i3c/ccc.h>
344 * dynamic address (RSTDAA CCC), we need to make sure no one is trying
401 * should send an ENTDAA CCC command and then add all devices
406 * @supports_ccc_cmd: should return true if the CCC command is supported, false
409 * all CCC commands are supported.
410 * @send_ccc_cmd: send a CCC command
441 * IRQ) and then send the ENEC CCC command (with the IBI flag set)
444 * @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI
/openbmc/linux/fs/unicode/
H A Dutf8-norm.c156 * defined. The CCC of a non-defined code point is 0.
159 * with a non-zero CCC that occur between two characters with
160 * a CCC of 0, or at the begin or end of a string.
161 * The unicode standard guarantees that all CCC values are
164 * Code points with CCC 0 are known as stoppers.
168 * The CCC of a decomposable character is the same as the CCC
172 * These do affect normalization, as they all have CCC 0.
433 u8c->ccc = STOPPER; in utf8ncursor()
454 * Characters are emitted if they match the current CCC in u8c->ccc.
455 * Hitting end-of-string while u8c->ccc == STOPPER means we're done,
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H A Dmkutf8data.c151 * defined. The CCC of a non-defined code point is 0.
154 * with a non-zero CCC that occur between two characters with
155 * a CCC of 0, or at the begin or end of a string.
156 * The unicode standard guarantees that all CCC values are
159 * Code points with CCC 0 are known as stoppers.
163 * The CCC of a decomposable character is the same as the CCC
167 * These do affect normalization, as they all have CCC 0.
1341 int ccc; member
1381 if (left->ccc != right->ccc) in nfdi_equal()
1398 if (left->ccc != right->ccc) in nfdicf_equal()
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/openbmc/qemu/hw/i3c/
H A Dtrace-events18 aspeed_i3c_device_transfer_ccc(uint32_t deviceid, uint8_t ccc) "I3C Dev[%u] transfer CCC 0x%" PRIx8
24 i3c_target_handle_ccc(uint8_t address, uint8_t ccc) "I3C target 0x%" PRIx8 " handling CCC 0x%" PRIx8
43 mock_target_new_ccc(uint8_t ccc) "I3C mock target handle CCC 0x%" PRIx8
50 remote_i3c_ccc_read(const char *name, uint32_t num_read, uint32_t num_to_read) "Remote I3C '%s' CCC…
H A Dcore.c173 /* If we're not in ENTDAA, a broadcast is the start of a new CCC. */ in i3c_do_start_transfer()
265 * Once they're handled, we pass the CCC up to the I3C target to do anything
274 /* Is this the start of a new CCC? */ in i3c_target_handle_ccc_write()
306 /* If this isn't the CCC byte, it's our new address. */ in i3c_target_handle_ccc_write()
337 /* If this message is a broadcast and no CCC has been found, grab it. */ in i3c_send()
339 bus->ccc = *data; in i3c_send()
343 * On any other CCC, the CCC is over on a RESTART or STOP, but ENTDAA in i3c_send()
346 if (bus->ccc == I3C_CCC_ENTDAA) { in i3c_send()
360 /* Targets should only NACK on a direct CCC. */ in i3c_send()
361 if (ret && !CCC_IS_DIRECT(bus->ccc)) { in i3c_send()
/openbmc/linux/Documentation/driver-api/i3c/
H A Dprotocol.rst121 I3C CCC commands
124 CCC (Common Command Code) commands are meant to be used for anything that is
127 CCC commands contain an 8-bit CCC ID describing the command that is executed.
132 payload is either sent by the master sending the command (write CCC command),
133 or sent by the slave receiving the command (read CCC command). Of course, read
135 Note that, when sending a CCC command to a specific device, the device address
139 from the CCC ID.
141 Note that vendors can use a dedicated range of CCC IDs for their own commands
172 using a broadcast CCC command.
/openbmc/qemu/include/hw/i3c/
H A Di3c.h118 * Handle a read CCC transmitted from a controller.
120 * The target can NACK the CCC if it does not support it.
125 * Handle a write CCC transmitted from a controller.
127 * The target can NACK the CCC if it does not support it.
142 /* CCC State tracking. */
168 uint8_t ccc; member
222 * I3C receives can only NACK on a CCC. The target should NACK a CCC it does not
H A Dremote-i3c.h19 * On an I3C private and CCC TX (controller -> target)
24 * On an I3C private and CCC RX (target -> controller)
/openbmc/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dcore.c192 struct i3c_ccc_cmd *ccc) in i3c_hci_send_ccc_cmd() argument
197 bool prefixed = raw && !!(ccc->id & I3C_CCC_DIRECT); in i3c_hci_send_ccc_cmd()
198 unsigned int nxfers = ccc->ndests + prefixed; in i3c_hci_send_ccc_cmd()
203 ccc->id, ccc->rnw, ccc->ndests, ccc->dests[0].payload.len); in i3c_hci_send_ccc_cmd()
214 ccc->id, true); in i3c_hci_send_ccc_cmd()
219 xfer[i].data = ccc->dests[i].payload.data; in i3c_hci_send_ccc_cmd()
220 xfer[i].data_len = ccc->dests[i].payload.len; in i3c_hci_send_ccc_cmd()
221 xfer[i].rnw = ccc->rnw; in i3c_hci_send_ccc_cmd()
222 ret = hci->cmd->prep_ccc(hci, &xfer[i], ccc->dests[i].addr, in i3c_hci_send_ccc_cmd()
223 ccc->id, raw); in i3c_hci_send_ccc_cmd()
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,mpfs-ccc.yaml4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
20 const: microchip,mpfs-ccc
31 The CCC PLL's have two input clocks. It is required that even if the input
72 compatible = "microchip,mpfs-ccc";
/openbmc/linux/drivers/power/supply/
H A Daxp20x_battery.c617 int ccc = info->constant_charge_current_max_ua; in axp20x_power_probe() local
624 /* Set max to unverified value to be able to set CCC */ in axp20x_power_probe()
625 axp20x_batt->max_ccc = ccc; in axp20x_power_probe()
627 if (ccc <= 0 || axp20x_set_constant_charge_current(axp20x_batt, in axp20x_power_probe()
628 ccc)) { in axp20x_power_probe()
631 ccc = 300000; in axp20x_power_probe()
632 axp20x_batt->max_ccc = ccc; in axp20x_power_probe()
633 axp20x_set_constant_charge_current(axp20x_batt, ccc); in axp20x_power_probe()
638 * Update max CCC to a valid value if battery info is present or set it in axp20x_power_probe()
/openbmc/linux/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c58 * mpfs_ccc_lock prevents anything else from writing to a fabric ccc
204 pll_hw->name = devm_kasprintf(dev, GFP_KERNEL, "ccc%s_pll%u", in mpfs_ccc_register_plls()
216 return dev_err_probe(dev, ret, "failed to register ccc id: %d\n", in mpfs_ccc_register_plls()
267 { .compatible = "microchip,mpfs-ccc", },
275 .name = "microchip-mpfs-ccc",
H A DMakefile5 obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs-ccc.o
/openbmc/linux/drivers/i3c/master/
H A Ddw-i3c-master.c681 struct i3c_ccc_cmd *ccc) in dw_i3c_ccc_set() argument
687 if (ccc->id & I3C_CCC_DIRECT) { in dw_i3c_ccc_set()
688 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); in dw_i3c_ccc_set()
698 cmd->tx_buf = ccc->dests[0].payload.data; in dw_i3c_ccc_set()
699 cmd->tx_len = ccc->dests[0].payload.len; in dw_i3c_ccc_set()
701 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) | in dw_i3c_ccc_set()
706 COMMAND_PORT_CMD(ccc->id) | in dw_i3c_ccc_set()
716 ccc->err = I3C_ERROR_M2; in dw_i3c_ccc_set()
723 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc) in dw_i3c_ccc_get() argument
729 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); in dw_i3c_ccc_get()
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H A Dsvc-i3c-master.c1286 /* cmd->xfer is NULL if I2C or CCC transfer */ in svc_i3c_master_start_xfer_locked()
1340 /* No software support for CCC commands targeting more than one slave */ in svc_i3c_master_supports_ccc_cmd()
1345 struct i3c_ccc_cmd *ccc) in svc_i3c_master_send_bdcast_ccc_cmd() argument
1347 unsigned int xfer_len = ccc->dests[0].payload.len + 1; in svc_i3c_master_send_bdcast_ccc_cmd()
1363 buf[0] = ccc->id; in svc_i3c_master_send_bdcast_ccc_cmd()
1364 memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len); in svc_i3c_master_send_bdcast_ccc_cmd()
1369 cmd->addr = ccc->dests[0].addr; in svc_i3c_master_send_bdcast_ccc_cmd()
1370 cmd->rnw = ccc->rnw; in svc_i3c_master_send_bdcast_ccc_cmd()
1391 struct i3c_ccc_cmd *ccc) in svc_i3c_master_send_direct_ccc_cmd() argument
1393 unsigned int xfer_len = ccc->dests[0].payload.len; in svc_i3c_master_send_direct_ccc_cmd()
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/openbmc/rest-dbus/resources/
H A Dstyle.css22 border: thin dashed #ccc;
35 border: thin solid #ccc;
/openbmc/linux/arch/mips/include/asm/
H A Dpgtable-bits.h203 * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
204 * 32-bit, R1 or earler: CCC D V G M A W R P
205 * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
206 * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
/openbmc/u-boot/arch/mips/include/asm/
H A Dpgtable-bits.h186 * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
187 * 32-bit, R1 or earler: CCC D V G M A W R P
188 * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
189 * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
/openbmc/qemu/tests/qtest/
H A Dremote-i3c-test.c216 * CMD is ignored due to this not being a CCC, and there is no defining in aspeed_i3c_send()
217 * byte, also because this isn't a CCC. in aspeed_i3c_send()
253 * CMD is ignored due to this not being a CCC, and there is no defining in aspeed_i3c_recv()
254 * byte, also because this isn't a CCC. in aspeed_i3c_recv()
315 * - the size of the CCC packet as a LE uint32 in add_targets_to_bus()
316 * - the CCC in add_targets_to_bus()
/openbmc/qemu/hw/misc/
H A Dmchp_pfsoc_ioscb.c239 memory_region_init_io(&s->ccc, OBJECT(s), &mchp_pfsoc_dummy_ops, s, in mchp_pfsoc_ioscb_realize()
240 "mchp.pfsoc.ioscb.ccc", IOSCB_CCC_REG_SIZE); in mchp_pfsoc_ioscb_realize()
241 memory_region_add_subregion(&s->container, IOSCB_CCC_BASE, &s->ccc); in mchp_pfsoc_ioscb_realize()
/openbmc/webui-vue/docs/.vuepress/components/colors/
H A Dcolors.scss13 border: 1px dashed #ccc;
/openbmc/linux/drivers/gpu/drm/armada/
H A Darmada_overlay.c354 #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8) in armada_overlay_set_property() macro
355 drm_to_overlay_state(state)->colorkey_yr = CCC(K2R(val)); in armada_overlay_set_property()
356 drm_to_overlay_state(state)->colorkey_ug = CCC(K2G(val)); in armada_overlay_set_property()
357 drm_to_overlay_state(state)->colorkey_vb = CCC(K2B(val)); in armada_overlay_set_property()
358 #undef CCC in armada_overlay_set_property()
/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/css/
H A Dscreen.css21 border: 1px solid #ccc;

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