| /openbmc/linux/arch/arm/mm/ |
| H A D | cache-fa.S | 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
68 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
70 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
90 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
96 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
98 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
127 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
132 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
134 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
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| H A D | proc-arm946.S | 57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
328 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| H A D | proc-xsc3.S | 149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
202 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
204 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
231 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
250 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
252 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
[all …]
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| H A D | cache-v6.S | 42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
145 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
150 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
|
| H A D | proc-arm940.S | 50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
167 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
275 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
281 mcr p15, 0, r0, c6, c5, 0
287 mcr p15, 0, r0, c6, c5, 1
319 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
320 mcr p15, 0, r0, c5, c0, 1
|
| H A D | proc-fa526.S | 108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
111 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
142 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
150 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
|
| H A D | cache-v4wt.S | 48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
70 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
122 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
|
| H A D | proc-arm925.S | 143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
197 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
207 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
242 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
266 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
403 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
| H A D | proc-arm926.S | 109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
364 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
| H A D | proc-mohawk.S | 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
178 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
202 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
318 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
361 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
|
| H A D | proc-xscale.S | 148 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
191 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
215 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
237 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
244 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
268 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
285 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
290 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
311 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
473 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
|
| H A D | tlb-v6.S | 50 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
86 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
|
| /openbmc/linux/arch/s390/crypto/ |
| H A D | chacha-s390.S | 467 #define C5 %v22 macro
519 VLR C5,K2
550 VAF C5,C5,D5
556 VX B5,B5,C5
588 VAF C5,C5,D5
594 VX B5,B5,C5
607 VSLDB C5,C5,C5,8
645 VAF C5,C5,D5
651 VX B5,B5,C5
683 VAF C5,C5,D5
[all …]
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| /openbmc/openbmc/meta-ibm/recipes-phosphor/logging/phosphor-logging/p10bmc/ |
| H A D | com.ibm.Hardware.Chassis.Model.Rainier2U_dev_callouts.json | 6 "LocationCode":"P0-C5",
35 "LocationCode":"P0-C5",
64 "LocationCode":"P0-C5",
93 "LocationCode":"P0-C5",
125 "LocationCode":"P0-C5",
154 "LocationCode":"P0-C5",
183 "LocationCode":"P0-C5",
212 "LocationCode":"P0-C5",
241 "LocationCode":"P0-C5",
270 "LocationCode":"P0-C5",
[all …]
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| H A D | com.ibm.Hardware.Chassis.Model.Rainier4U_dev_callouts.json | 6 "LocationCode":"P0-C5",
35 "LocationCode":"P0-C5",
64 "LocationCode":"P0-C5",
93 "LocationCode":"P0-C5",
125 "LocationCode":"P0-C5",
154 "LocationCode":"P0-C5",
183 "LocationCode":"P0-C5",
212 "LocationCode":"P0-C5",
241 "LocationCode":"P0-C5",
270 "LocationCode":"P0-C5",
[all …]
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| H A D | com.ibm.Hardware.Chassis.Model.Bonnell_dev_callouts.json | 6 "LocationCode":"P0-C5",
22 "LocationCode":"P0-C5",
42 "LocationCode":"P0-C5",
59 "LocationCode":"P0-C5",
76 "LocationCode":"P0-C5",
93 "LocationCode":"P0-C5",
112 "LocationCode":"P0-C5",
129 "LocationCode":"P0-C5",
148 "LocationCode":"P0-C5",
170 "LocationCode":"P0-C5",
[all …]
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| /openbmc/qemu/target/xtensa/core-de212/ |
| H A D | gdb-config.c.inc | 123 …c:03:60:55:11:03:52:c5:20:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:0…
125 …c:03:60:55:11:03:52:c5:24:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:0…
127 …c:03:60:55:11:03:52:c5:28:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:0…
131 …0:55:11:03:52:c5:a0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:6…
133 …0:55:11:03:52:c5:a4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:6…
135 …0:55:11:03:52:c5:b0:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:6…
137 …0:55:11:03:52:c5:b4:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:6…
139 …0:55:11:03:52:c5:b8:03:52:d5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:6…
143 …0:03:60:55:11:03:52:c5:04:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:0…
145 …0:03:60:55:11:03:52:c5:08:03:60:65:40:03:62:64:00:03:52:24:01:03:62:24:02","03:52:64:01:03:62:64:0…
[all …]
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| /openbmc/linux/arch/arm/include/asm/hardware/ |
| H A D | cp14.h | 47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
62 #define RCP14_DBGBVR5() MRC14(0, c0, c5, 4)
78 #define RCP14_DBGBCR5() MRC14(0, c0, c5, 5)
94 #define RCP14_DBGWVR5() MRC14(0, c0, c5, 6)
110 #define RCP14_DBGWCR5() MRC14(0, c0, c5, 7)
127 #define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1)
142 #define RCP14_DBGPRSR() MRC14(0, c1, c5, 4)
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
167 #define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
183 #define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5)
[all …]
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| /openbmc/qemu/tests/tcg/hexagon/ |
| H A D | preg_alias.c | 46 "%0 = C5:4\n" in preg_alias_pair()
79 uint32_t c5; in creg_alias_pair() local
81 asm ("c5:4 = %5\n\t" in creg_alias_pair()
86 "%4 = c5\n\t" in creg_alias_pair()
88 "=r"(pregs->pregs.p2), "=r"(pregs->pregs.p3), "=r"(c5) in creg_alias_pair()
90 : "c4", "c5", "p0", "p1", "p2", "p3"); in creg_alias_pair()
92 check32(c5, 0xdeadbeef); in creg_alias_pair()
|
| /openbmc/linux/arch/arm/include/asm/ |
| H A D | tlbflush.h | 323 tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero); in __local_flush_tlb_all()
370 tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero); in __local_flush_tlb_mm()
376 tlb_op(TLB_V6_I_ASID, "c8, c5, 2", asid); in __local_flush_tlb_mm()
424 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr); in __local_flush_tlb_page()
426 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); in __local_flush_tlb_page()
431 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", uaddr); in __local_flush_tlb_page()
479 tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr); in __local_flush_tlb_kernel_page()
481 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); in __local_flush_tlb_kernel_page()
485 tlb_op(TLB_V6_I_PAGE, "c8, c5, 1", kaddr); in __local_flush_tlb_kernel_page()
534 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); in __local_flush_bp_all()
[all …]
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| H A D | dcc.h | 20 asm volatile("mrc p14, 0, %0, c0, c5, 0 @ read comms data reg" in __dcc_getchar()
29 asm volatile("mcr p14, 0, %0, c0, c5, 0 @ write a char" in __dcc_putchar()
|
| /openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/css/ |
| H A D | jquery.treetable.theme.default.css | 36 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
40 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
46 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
50 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
59 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
63 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
|
| H A D | jquery.treetable.theme.toaster.css | 10 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
14 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
20 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
24 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
33 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
37 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
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| /openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/ |
| H A D | jquery.treetable.theme.toaster.css | 38 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
42 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
48 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
52 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
61 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
65 …4LLLpc+Lpsbxt3IveRKdPVxXeF60vWdm7Obwu2o26/uNu5p7ofcn8w0nymeWTNz0MPIQ+BR5dE/C5+VMGvfrH5PQ0+BZ7XnIy9…
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | nvidia,tegra194-pcie.yaml | 128 5: C5
137 5 : C5
159 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
160 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
182 if the platform has one such slot, e.g., x16 slot owned by C5 controller
187 if the platform has one such slot, e.g., x16 slot owned by C5 controller
|