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/openbmc/linux/arch/sh/kernel/cpu/sh3/
H A Dswsusp.S59 ! BL=0: R7->R0 is bank0
80 ! BL=0: R7->R0 is bank0
105 ! BL=0: R7->R0 is bank0
116 jsr @k1 ! switch to bank0 and save all regs
119 ! BL=0: R7->R0 is bank0
/openbmc/linux/drivers/bus/
H A Duniphier-system-bus.c15 #define UNIPHIER_SBC_BASE 0x100 /* base address of bank0 space */
17 #define UNIPHIER_SBC_CTRL0 0x200 /* timing parameter 0 of bank0 */
18 #define UNIPHIER_SBC_CTRL1 0x204 /* timing parameter 1 of bank0 */
19 #define UNIPHIER_SBC_CTRL2 0x208 /* timing parameter 2 of bank0 */
20 #define UNIPHIER_SBC_CTRL3 0x20c /* timing parameter 3 of bank0 */
21 #define UNIPHIER_SBC_CTRL4 0x300 /* timing parameter 4 of bank0 */
127 * swapped. In this case, bank0 and bank1 should be swapped as well. in uniphier_system_bus_check_boot_swap()
/openbmc/u-boot/arch/nds32/cpu/n1213/ag101/
H A Dlowlevel_init.S95 * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
125 /* SRAM bank0 config */
220 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
222 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
223 * and the FLASH is connected to BANK0.
225 * BANK0 (0x00000000) while memory remapping was skipped.
228 * a FLASH connected to bank0.
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Drockchip,gpio-bank.yaml16 - rockchip,rk3188-gpio-bank0
65 compatible = "rockchip,rk3188-gpio-bank0";
/openbmc/u-boot/doc/device-tree-bindings/pinctrl/
H A Drockchip,pinctrl.txt54 - compatible: "rockchip,rk3188-gpio-bank0"
55 - reg: second element: separate pull register for rk3188 bank0, use
130 compatible = "rockchip,rk3188-gpio-bank0";
/openbmc/linux/drivers/leds/
H A Dleds-tca6507.c18 * are named MASTER, BANK0 and BANK1.
24 * align with the two levels BANK0 and BANK1. This driver does not
62 * Each bank (BANK0 and BANK1) has two usage counts - LEDs using the
86 #define TCA6507_LS_LED_PWM0 0x2 /* Output LOW with Bank0 rate */
90 #define TCA6507_LS_BLINK0 0x6 /* Blink at Bank0 rate */
103 BANK0, enumerator
301 case BANK0: in set_level()
410 for (i = MASTER; i >= BANK0; i--) { in led_prepare()
450 for (i = BANK0; i <= BANK1; i++) { in led_prepare()
/openbmc/linux/drivers/soundwire/
H A Ddebugfs.c74 ret += scnprintf(buf + ret, RD_BUF - ret, "Bank0\n"); in sdw_slave_reg_show()
116 /* DPi Bank0 registers */ in sdw_slave_reg_show()
117 ret += scnprintf(buf + ret, RD_BUF - ret, "Bank0\n"); in sdw_slave_reg_show()
/openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-memory.json488 "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
552 "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
616 "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
680 "EventName": "UNC_M_RD_CAS_RANK3.BANK0",
744 "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
808 "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
872 "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
936 "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
1110 "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
1174 "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
[all …]
/openbmc/linux/arch/sh/kernel/
H A Drelocate_kernel.S57 /* switch to bank0 and save r7->r0 */
89 /* make sure bank0 is active and restore r0->r7 */
118 /* switch back to bank0 */
/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3399.c62 /* The bank0:16 and bank1:32 pins are located in PMU */ in rk3399_calc_pull_reg_and_bit()
93 /* The bank0:16 and bank1:32 pins are located in PMU */ in rk3399_calc_drv_reg_and_bit()
/openbmc/u-boot/board/logicpd/zoom1/
H A Dconfig.mk9 # 8000'0000 (bank0)
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
H A Dkwbimage-is2.cfg141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
H A Dkwbimage-ns2l.cfg141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
/openbmc/u-boot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg141 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
142 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
/openbmc/linux/Documentation/admin-guide/gpio/
H A Dgpio-sim.rst96 bank0 {
100 gpio-sim,label = "dt-bank0";
/openbmc/linux/drivers/iommu/
H A Dmtk_iommu.c377 /* Tlb flush all always is in bank0. */ in mtk_iommu_tlb_flush_all()
1021 const struct mtk_iommu_bank_data *bank0 = &data->bank[0]; in mtk_iommu_hw_init() local
1025 * Global control settings are in bank0. May re-init these global registers in mtk_iommu_hw_init()
1026 * since no sure if there is bank0 consumers. in mtk_iommu_hw_init()
1032 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
1035 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
1044 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG); in mtk_iommu_hw_init()
1047 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS); in mtk_iommu_hw_init()
1049 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS); in mtk_iommu_hw_init()
1053 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_hw_init()
[all …]
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg152 # bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
153 # bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
H A Dkwbimage-memphis.cfg167 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
168 # bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-msc-sm2s-14N0600E.dtsi12 reg = <0x0 0x40000000 0 0x80000000>; /* bank0, 2GiB */
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json545 "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
712 "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
879 "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
1046 "EventName": "UNC_M_RD_CAS_RANK3.BANK0",
1213 "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
1380 "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
1547 "EventName": "UNC_M_RD_CAS_RANK6.BANK0",
1714 "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
1992 "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
2159 "EventName": "UNC_M_WR_CAS_RANK1.BANK0",
[all …]
/openbmc/u-boot/board/freescale/t102xrdb/
H A Dt102xrdb.c309 if (!strcmp(argv[1], "bank0")) in switch_cmd()
324 "for bank0/bank4/sd/emmc switch control in runtime",
/openbmc/linux/arch/sh/kernel/cpu/shmobile/
H A Dsleep.S62 /* make sure bank0 is selected, save low registers */
347 /* switch to bank0, restore low registers */
/openbmc/linux/drivers/iio/adc/
H A Dcpcap-adc.c128 /* Bank0 channels */
148 /* Remuxed channels using bank0 entries */
221 /* Bank0 */
247 /* Bank0 */
357 /* Bank0 */
/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PB82 => run boot_bank0 (boot from NOR bank0)
151 For bank0

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