| /openbmc/linux/drivers/staging/media/atomisp/pci/ |
| H A D | ia_css_env.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
27 * CSS-API host-code by the environment in which the CSS-API code runs.
53 /** Store an 8 bit value into an address in the CSS HW address space.
54 The address must be an 8 bit aligned address. */
56 /** Store a 16 bit value into an address in the CSS HW address space.
57 The address must be a 16 bit aligned address. */
59 /** Store a 32 bit value into an address in the CSS HW address space.
60 The address must be a 32 bit aligned address. */
62 /** Load an 8 bit value from an address in the CSS HW address
63 space. The address must be an 8 bit aligned address. */
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| /openbmc/linux/tools/testing/selftests/mm/ |
| H A D | mremap_test.c | 1 // SPDX-License-Identifier: GPL-2.0
41 _1KB = 1ULL << 10, /* 1KB -> not page aligned */
80 -1, 0); in is_remap_region_valid()
122 * Using /proc/self/maps, assert that the specified address range is contained
133 while (getline(&line, &len, maps_fp) != -1) { in is_range_mapped()
134 char *first = strtok(line, "- "); in is_range_mapped()
136 char *second = strtok(NULL, "- "); in is_range_mapped()
162 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); in mremap_expand_merge()
201 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); in mremap_expand_merge_offset()
228 * Returns the start address of the mapping on success, else returns
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| /openbmc/u-boot/include/ |
| H A D | memalign.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
27 * 1) The beginning of the array can be advanced enough to be aligned.
29 * 2) The size of the aligned portion of the array is a multiple of the minimum
32 * 3) The aligned portion contains enough space for the original number of
35 * The macro then creates a pointer to the aligned portion of this array and
36 * assigns to the pointer the address of the first element in the aligned
49 * 1) The resulting buffer is guaranteed to be aligned to the value of
54 * if you want the address of the buffer, which you probably do, to pass it
56 * In the macro case it will be the address of the pointer, not the address
58 * would be the address of the buffer. So if you are replacing hard coded
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| /openbmc/linux/arch/sparc/include/asm/ |
| H A D | hypervisor.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 * -----------------------------------------------
23 * -----------------------------------------------
25 * The second type are "hyper-fast traps" which encode the function
27 * numbers > 0x80. The register usage for hyper-fast traps is as
30 * -----------------------------------------------
36 * -----------------------------------------------
44 * defined below. So, for example, if a hyper-fast trap takes
49 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
63 #define HV_ENORADDR 2 /* Invalid real address */
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| /openbmc/u-boot/doc/ |
| H A D | README.displaying-bmps | 1 If you are experiencing hangups/data-aborts when trying to display a BMP image,
6 make sure all data is properly aligned, and in many situations simply choosing
7 a 32 bit aligned address is enough to ensure proper alignment. This is not
11 BMP images have a header that starts with 2 byte-size fields followed by mostly
23 When placed in an aligned address such as 0x80a00000, char signature offsets
25 0x80a00006, and so on...). When these fields are accessed by U-Boot, a 32 bit
26 access is generated at a non-32-bit-aligned address, causing a data abort.
27 The proper alignment for BMP images is therefore: 32-bit-aligned-address + 2.
|
| /openbmc/linux/arch/riscv/lib/ |
| H A D | uaccess.S | 2 #include <asm-generic/export.h>
4 #include <asm/asm-extable.h>
21 * Save the terminal address which will be used to compute the number
28 * a0 - start of uncopied dst
29 * a1 - start of uncopied src
30 * a2 - size
31 * t0 - end of uncopied dst
43 * Copy first bytes until dst is aligned to word boundary.
44 * a0 - start of dst
45 * t1 - start of aligned dst
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| /openbmc/linux/arch/arm/mm/ |
| H A D | tlb-v7.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v7.S
5 * Copyright (C) 1997-2002 Russell King
14 #include <asm/asm-offsets.h>
17 #include "proc-macros.S"
19 .arch armv7-a
24 * Invalidate a range of TLB entries in the specified address space.
26 * - start - start address (may not be aligned)
27 * - end - end address (exclusive, may not be aligned)
28 * - vma - vm_area_struct describing address range
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| H A D | tlb-v6.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/tlb-v6.S
5 * Copyright (C) 1997-2002 Russell King
12 #include <asm/asm-offsets.h>
16 #include "proc-macros.S"
25 * Invalidate a range of TLB entries in the specified address space.
27 * - start - start address (may not be aligned)
28 * - end - end address (exclusive, may not be aligned)
29 * - vma - vm_area_struct describing address range
32 * - the "Invalidate single entry" instruction will invalidate
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| /openbmc/linux/arch/alpha/lib/ |
| H A D | ev6-memset.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
48 * undertake a major re-write to interleave the constant materialization
49 * with other parts of the fall-through code. This is important, even
58 addq $18,$16,$6 # E : max address to write to
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| /openbmc/linux/tools/testing/memblock/tests/ |
| H A D | alloc_helpers_api.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * aligned address:
9 * | +-----------+ |
11 * +----------+-----------+---------+
14 * Aligned min_addr
16 * Expect to allocate a cleared region at the minimal memory address.
28 min_addr = memblock_end_of_DRAM() - SMP_CACHE_BYTES; in alloc_from_simple_generic_check()
35 ASSERT_EQ(rgn->size, size); in alloc_from_simple_generic_check()
36 ASSERT_EQ(rgn->base, min_addr); in alloc_from_simple_generic_check()
47 * A test that tries to allocate a memory region above a certain address.
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| /openbmc/u-boot/drivers/net/pfe_eth/ |
| H A D | pfe_hw.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
35 (u32)TMU_DMEM_BASE_ADDR(pfe_pe_id - TMU0_ID); in pfe_lib_init()
37 (u32)TMU_IMEM_BASE_ADDR(pfe_pe_id - TMU0_ID); in pfe_lib_init()
51 * @param[in] mem_access_addr DMEM destination address (must be 32bit
52 * aligned)
53 * @param[in] src Buffer source address
92 * @param[in] dst DMEM destination address (must be 32bit
93 * aligned)
94 * @param[in] src Buffer source address
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| /openbmc/linux/arch/xtensa/lib/ |
| H A D | checksum.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 * This function assumes 2- or 4-byte alignment. Other alignments will fail!
32 /* ONES_ADD converts twos-complement math to ones-complement. */
44 * is aligned on either a 2-byte or 4-byte boundary.
48 bnez a5, 8f /* branch if 2-byte aligned */
49 /* Fall-through on common case, 4-byte alignment */
51 srli a5, a3, 5 /* 32-byte chunks */
57 add a5, a5, a2 /* a5 = end of last 32-byte chunk */
81 extui a5, a3, 2, 3 /* remaining 4-byte chunks */
87 add a5, a5, a2 /* a5 = end of last 4-byte chunk */
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| /openbmc/linux/sound/soc/fsl/ |
| H A D | fsl_dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC
15 __be32 clndar; /* Current link descriptor address register */
17 __be32 sar; /* Source address register */
19 __be32 dar; /* Destination address register */
21 __be32 enlndar; /* Next link descriptor extended address reg */
22 __be32 nlndar; /* Next link descriptor address register */
25 __be32 clsdar; /* Current list descriptor address register */
26 __be32 enlsdar; /* Next list descriptor extended address reg */
27 __be32 nlsdar; /* Next list descriptor address register */
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| /openbmc/qemu/accel/tcg/ |
| H A D | ldst_atomicity.c.inc | 6 * SPDX-License-Identifier: GPL-2.0-or-later
9 * See the COPYING file in the top-level directory.
12 #include "host/load-extract-al16-al8.h.inc"
13 #include "host/store-insert-al16.h.inc"
27 * examined separately for atomicity, return -lg2.
33 MemOp half = size ? size - 1 : 0;
47 tmp = (1 << size) - 1;
63 * Both halves are naturally aligned and atomic.
68 * One of the pair crosses the boundary, and is non-atomic.
71 atmax = -half;
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| /openbmc/qemu/tests/uefi-test-tools/UefiTestToolsPkg/Include/Guid/ |
| H A D | BiosTablesTest.h | 2 Expose the address(es) of the ACPI RSD PTR table(s) and the SMBIOS entry
3 point(s) in a MB-aligned structure to the hypervisor.
5 The hypervisor locates the MB-aligned structure based on the signature GUID
7 address(es) are retrieved, the hypervisor may perform various ACPI and SMBIOS
18 <http://opensource.org/licenses/bsd-license.php>.
41 // aligned at a 1MB boundary.
46 // The signature GUID is written to the MB-aligned structure from
50 // bit-flipping occurs in order not to store the actual GUID in any UEFI
57 // Rsdp10 is the guest-physical address of the ACPI 1.0 specification RSD PTR
58 // table, in 8-byte little endian representation. Rsdp20 is the same, for the
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| /openbmc/linux/Documentation/arch/sparc/oradax/ |
| H A D | dax-hv-api.txt | 3 Publication date 2017-09-25 08:21
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
16 live-migration and other system management activities.
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
45 …device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device
51 36.1.1.1. "ORCL,sun4v-dax" Device Compatibility
54 • No-op/Sync
81 36.1.1.2. "ORCL,sun4v-dax-fc" Device Compatibility
82 … "ORCL,sun4v-dax-fc" is compatible with the "ORCL,sun4v-dax" interface, and includes additional CCB
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | nand_spl_loaders.c | 6 /* offs has to be aligned to a page address! */ in nand_spl_load_image()
8 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE; in nand_spl_load_image()
18 * When offs is not aligned to page address the in nand_spl_load_image()
26 dst = (void *)((int)dst - page_offset); in nand_spl_load_image()
46 * Temporary storage for non NAND page aligned and non NAND page sized
54 * nand_spl_read_block - Read data from physical eraseblock into a buffer
58 * @dst: Address of the destination buffer
86 * Non page aligned reads go to the scratch buffer. in nand_spl_read_block()
87 * Page aligned reads go directly to the destination. in nand_spl_read_block()
91 read = min(len, CONFIG_SYS_NAND_PAGE_SIZE - offset); in nand_spl_read_block()
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| /openbmc/linux/arch/s390/include/asm/ |
| H A D | qdio.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define QDIO_MAX_BUFFERS_MASK (QDIO_MAX_BUFFERS_PER_Q - 1)
27 * struct qdesfmt0 - queue descriptor, format 0
28 * @sliba: absolute address of storage list information block
29 * @sla: absolute address of storage list
30 * @slsba: absolute address of storage list state block
51 * struct qdr - queue description record (QDR)
58 * @qiba: absolute address of queue information block
89 * struct qib - queue information block (QIB)
94 * @isliba: logical address of first input SLIB
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| /openbmc/u-boot/arch/arm/lib/ |
| H A D | cache-pl310.c | 1 // SPDX-License-Identifier: GPL-2.0+
18 writel(0, &pl310->pl310_cache_sync); in pl310_cache_sync()
25 assoc_16 = readl(&pl310->pl310_aux_ctrl) & in pl310_background_op_all_ways()
32 way_mask = (1 << associativity) - 1; in pl310_background_op_all_ways()
43 pl310_background_op_all_ways(&pl310->pl310_inv_way); in v7_outer_cache_inval_all()
48 pl310_background_op_all_ways(&pl310->pl310_clean_inv_way); in v7_outer_cache_flush_all()
51 /* Flush(clean invalidate) memory from start to stop-1 */
58 * Align to the beginning of cache-line - this ensures that in v7_outer_cache_flush_range()
61 start &= ~(line_size - 1); in v7_outer_cache_flush_range()
64 writel(pa, &pl310->pl310_clean_inv_line_pa); in v7_outer_cache_flush_range()
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| /openbmc/linux/include/uapi/linux/ |
| H A D | vhost_types.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 /* Userspace interface for in-kernel virtio accelerators. */
26 int fd; /* Pass -1 to unbind from file. */
35 /* Whether log address is valid. If set enables logging. */
40 /* Used structure address. Must be 32 bit aligned */
42 /* Available structure address. Must be 16 bit aligned */
46 * address. Address must be 32 bit aligned. */
120 /* All region addresses and sizes must be 4K aligned. */
132 * Used by QEMU userspace to ensure a consistent vhost-scsi ABI.
134 * ABI Rev 0: July 2012 version starting point for v3.6-rc merge candidate +
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| /openbmc/qemu/include/standard-headers/linux/ |
| H A D | vhost_types.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 /* Userspace interface for in-kernel virtio accelerators. */
14 #include "standard-headers/linux/types.h"
16 #include "standard-headers/linux/virtio_config.h"
17 #include "standard-headers/linux/virtio_ring.h"
26 int fd; /* Pass -1 to unbind from file. */
35 /* Whether log address is valid. If set enables logging. */
40 /* Used structure address. Must be 32 bit aligned */
42 /* Available structure address. Must be 16 bit aligned */
46 * address. Address must be 32 bit aligned. */
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| /openbmc/qemu/include/exec/ |
| H A D | memop.h | 8 * See the COPYING file in the top-level directory.
15 #include "qemu/host-utils.h"
28 MO_SIGN = 0x08, /* Sign-extended, otherwise zero-extended. */
49 * do_unaligned_access hook if the guest address is not aligned.
51 * Some architectures (e.g. ARMv8) need the address which is aligned
53 * Some architectures (e.g. SPARCv9) need an address which is aligned,
59 * - unaligned access permitted (MO_UNALN).
60 * - an alignment to the size of an access (MO_ALIGN);
61 * - an alignment to a specified size, which may be more or less than
77 * MO_ATOM_IFALIGN: the operation must be single-copy atomic if it
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | psp_gfx_if.h | 46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
57 /*-----------------------------------------------------------------------------
64 * SRBM-to-PSP mailbox registers (total 8 registers).
108 /* PSP boot config sub-commands */
125 …hy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligne…
126 …uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binar…
128 …_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned…
129 …uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
151 … buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned…
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| /openbmc/linux/arch/mips/include/asm/ |
| H A D | maar.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 * platform_maar_init() - perform platform-level MAAR configuration
18 * MAAR pairs as required, from 0 up to the maximum of num_pairs-1, and returns
28 * write_maar_pair() - write to a pair of MAARs
30 * @lower: The lowest address that the MAAR pair will affect. Must be
31 * aligned to a 2^16 byte boundary.
32 * @upper: The highest address that the MAAR pair will affect. Must be
33 * aligned to one byte before a 2^16 byte boundary.
52 * Write the upper address & attributes (both MIPS_MAAR_VL and in write_maar_pair()
65 /* Write the lower address & attributes */ in write_maar_pair()
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| /openbmc/linux/Documentation/core-api/ |
| H A D | unaligned-memory-access.rst | 23 from an address that is not evenly divisible by N (i.e. addr % N != 0).
24 For example, reading 4 bytes of data from address 0x10004 is fine, but
25 reading 4 bytes of data from address 0x10005 would be an unaligned memory
32 which will compile to multiple-byte memory access instructions, namely when
40 When accessing N bytes of memory, the base memory address must be evenly
59 - Some architectures are able to perform unaligned memory accesses
61 - Some architectures raise processor exceptions when unaligned accesses
64 - Some architectures raise processor exceptions when unaligned accesses
67 - Some architectures are not capable of unaligned memory access, but will
94 starting at address 0x10000. With a basic level of understanding, it would
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