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Searched full:auxclk (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-ivi-audio.yaml25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
31 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
32 | |-> MCASP0_AUXCLK ---> McASP0.auxclk
38 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
39 | |-> MCASP0_AUXCLK ---> McASP0.auxclk
75 - description: AUXCLK clock for McASP used by CPB audio
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
81 - description: AUXCLK clock for McASP used by IVI audio
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
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H A Dti,j721e-cpb-audio.yaml20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
25 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
29 PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
34 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
84 - description: AUXCLK clock for McASP used by CPB audio
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
93 - const: cpb-mcasp-auxclk
94 - const: cpb-mcasp-auxclk-48000
95 - const: cpb-mcasp-auxclk-44100
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H A Ddavinci-mcasp-audio.yaml126 auxclk-fs-ratio:
/openbmc/u-boot/board/ti/panda/
H A Dpanda.c212 u32 auxclk, altclksrc; in misc_init_r() local
227 auxclk = readl(&scrm->auxclk3); in misc_init_r()
229 auxclk &= ~AUXCLK_SRCSELECT_MASK; in misc_init_r()
230 auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT; in misc_init_r()
232 auxclk &= ~AUXCLK_CLKDIV_MASK; in misc_init_r()
233 auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT; in misc_init_r()
235 auxclk |= AUXCLK_ENABLE_MASK; in misc_init_r()
237 writel(auxclk, &scrm->auxclk3); in misc_init_r()
242 auxclk = readl(&scrm->auxclk1); in misc_init_r()
244 auxclk &= ~AUXCLK_SRCSELECT_MASK; in misc_init_r()
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/openbmc/u-boot/board/gumstix/duovero/
H A Dduovero.c222 u32 auxclk, altclksrc; in ehci_hcd_init() local
229 auxclk = readl(&scrm->auxclk3); in ehci_hcd_init()
231 auxclk &= ~AUXCLK_SRCSELECT_MASK; in ehci_hcd_init()
232 auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT; in ehci_hcd_init()
234 auxclk &= ~AUXCLK_CLKDIV_MASK; in ehci_hcd_init()
235 auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT; in ehci_hcd_init()
237 auxclk |= AUXCLK_ENABLE_MASK; in ehci_hcd_init()
238 writel(auxclk, &scrm->auxclk3); in ehci_hcd_init()
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt40 auxclk
41 Describes the AUXCLK output of the PLL. The node name must be "auxclk".
71 pll0_auxclk: auxclk {
H A Dda8xx-cfgchip.txt16 - clock-names: shall be "fck", "usb_refclkin", "auxclk"
63 clock-names = "fck", "usb_refclkin", "auxclk";
/openbmc/u-boot/board/ti/omap5_uevm/
H A Devm.c157 int auxclk; in enable_host_clocks() local
176 auxclk = readl((*prcm)->scrm_auxclk1); in enable_host_clocks()
178 auxclk |= AUXCLK_ENABLE_MASK; in enable_host_clocks()
179 writel(auxclk, (*prcm)->scrm_auxclk1); in enable_host_clocks()
/openbmc/linux/drivers/pci/controller/dwc/
H A Dpcie-visconti.c34 struct clk *auxclk; member
269 pcie->auxclk = devm_clk_get(dev, "aux"); in visconti_get_resources()
270 if (IS_ERR(pcie->auxclk)) in visconti_get_resources()
271 return dev_err_probe(dev, PTR_ERR(pcie->auxclk), in visconti_get_resources()
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62x-sk-hdmi-audio.dtso35 auxclk-fs-ratio = <2177>;
H A Dk3-j721e-common-proc-board.dts123 clock-names = "cpb-mcasp-auxclk",
124 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
825 auxclk-fs-ratio = <256>;
H A Dk3-am625-beagleplay.dts897 auxclk-fs-ratio = <2177>;
/openbmc/linux/drivers/clk/davinci/
H A Dpll.c391 * and will be the parent clock to the AUXCLK, SYSCLKBP and in davinci_pll_clk_register()
538 * davinci_pll_auxclk_register - Register bypass clock (AUXCLK)
811 child = of_get_child_by_name(node, "auxclk"); in of_davinci_pll_init()
/openbmc/linux/sound/soc/ti/
H A Ddavinci-mcasp.h303 #define MCASP_CLKDIV_AUXCLK 0 /* HCLK divider from AUXCLK */
H A Dj721e-evm.c642 ret = j721e_get_clocks(priv->dev, &domain->mcasp, "cpb-mcasp-auxclk"); in j721e_soc_probe_cpb()
754 ret = j721e_get_clocks(priv->dev, &domain->mcasp, "ivi-mcasp-auxclk"); in j721e_soc_probe_ivi()
H A Ddavinci-mcasp.c695 /* Select AUXCLK as HCLK */ in davinci_mcasp_set_sysclk()
702 * the same clock - coming via AUXCLK. in davinci_mcasp_set_sysclk()
1955 if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0) in davinci_mcasp_get_config()
/openbmc/u-boot/arch/arm/dts/
H A Dda850.dtsi101 pll0_auxclk: auxclk {
346 clock-names = "fck", "usb_refclkin", "auxclk";
/openbmc/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi147 pll0_auxclk: auxclk {
392 clock-names = "fck", "usb_refclkin", "auxclk";
/openbmc/linux/drivers/gpu/drm/msm/dp/
H A Ddp_catalog.c296 pr_info("AUXCLK regs\n"); in dp_catalog_dump_regs()
/openbmc/linux/drivers/tty/
H A Dsynclink_gt.c3809 * 01 auxclk enable (0 = disable) in enable_loopback()
4092 * 01 0 = auxclk disabled in async_mode()
4280 * 01 auxclk enable in sync_mode()