/openbmc/linux/arch/arm64/mm/ |
H A D | context.c | 38 #define ctxid2asid(asid) ((asid) & ~ASID_MASK) argument 39 #define asid2ctxid(asid, genid) ((asid) | (genid)) argument 44 u32 asid; in get_cpu_asid_bits() local 50 pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n", in get_cpu_asid_bits() 54 asid = 8; in get_cpu_asid_bits() 57 asid = 16; in get_cpu_asid_bits() 60 return asid; in get_cpu_asid_bits() 66 u32 asid = get_cpu_asid_bits(); in verify_cpu_asid_bits() local 68 if (asid < asid_bits) { in verify_cpu_asid_bits() 70 * We cannot decrease the ASID size at runtime, so panic if we support in verify_cpu_asid_bits() [all …]
|
/openbmc/linux/arch/csky/mm/ |
H A D | asid.c | 3 * Generic ASID allocator. 14 #include <asm/asid.h> 21 #define asid2idx(info, asid) (((asid) & ~ASID_MASK(info)) >> (info)->ctxt_shift) argument 27 u64 asid; in flush_context() local 29 /* Update the list of reserved ASIDs and the ASID bitmap. */ in flush_context() 33 asid = atomic64_xchg_relaxed(&active_asid(info, i), 0); in flush_context() 38 * ASID, as this is the only trace we have of in flush_context() 41 if (asid == 0) in flush_context() 42 asid = reserved_asid(info, i); in flush_context() 43 __set_bit(asid2idx(info, asid), info->map); in flush_context() [all …]
|
/openbmc/linux/arch/arm/mm/ |
H A D | context.c | 27 * | process ID | ASID | 32 * The ASID is used to tag entries in the CPU caches and TLBs. 56 u64 context_id, asid; in a15_erratum_get_cpumask() local 65 * running the same ASID as the one being invalidated. in a15_erratum_get_cpumask() 67 asid = per_cpu(active_asids, cpu).counter; in a15_erratum_get_cpumask() 68 if (asid == 0) in a15_erratum_get_cpumask() 69 asid = per_cpu(reserved_asids, cpu); in a15_erratum_get_cpumask() 70 if (context_id == asid) in a15_erratum_get_cpumask() 79 * With LPAE, the ASID and page tables are updated atomicly, so there is 80 * no need for a reserved set of tables (the active ASID tracking prevents [all …]
|
/openbmc/linux/arch/arc/include/asm/ |
H A D | mmu_context.h | 10 * -Major rewrite of Core ASID allocation routine get_new_mmu_context 23 /* ARC ASID Management 25 * MMU tags TLBs with an 8-bit ASID, avoiding need to flush the TLB on 28 * ASID is managed per cpu, so task threads across CPUs can have different 29 * ASID. Global ASID management is needed if hardware supports TLB shootdown 32 * Each task is assigned unique ASID, with a simple round-robin allocator 36 * A new allocation cycle, post rollover, could potentially reassign an ASID 37 * to a different task. Thus the rule is to refresh the ASID in a new cycle. 38 * The 32 bit @asid_cpu (and mm->asid) have 8 bits MMU PID and rest 24 bits 49 #define asid_mm(mm, cpu) mm->context.asid[cpu] [all …]
|
/openbmc/linux/arch/riscv/mm/ |
H A D | tlbflush.c | 18 unsigned long asid) in local_flush_tlb_range_threshold_asid() argument 24 local_flush_tlb_all_asid(asid); in local_flush_tlb_range_threshold_asid() 29 local_flush_tlb_page_asid(start, asid); in local_flush_tlb_range_threshold_asid() 35 unsigned long size, unsigned long stride, unsigned long asid) in local_flush_tlb_range_asid() argument 38 local_flush_tlb_page_asid(start, asid); in local_flush_tlb_range_asid() 40 local_flush_tlb_all_asid(asid); in local_flush_tlb_range_asid() 42 local_flush_tlb_range_threshold_asid(start, size, stride, asid); in local_flush_tlb_range_asid() 65 unsigned long asid; member 75 local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid); in __ipi_flush_tlb_range_asid() 83 unsigned long asid = FLUSH_TLB_NO_ASID; in __flush_tlb_range() local [all …]
|
H A D | context.c | 69 /* Update the list of reserved ASIDs and the ASID bitmap. */ in __flush_context() 88 /* Mark ASID #0 as used because it is used at boot-time */ in __flush_context() 99 unsigned long asid, ver = atomic_long_read(¤t_version); in __new_context() local 123 * Allocate a free ASID. If we can't find one then increment in __new_context() 126 asid = find_next_zero_bit(context_asid_map, num_asids, cur_idx); in __new_context() 127 if (asid != num_asids) in __new_context() 137 asid = find_next_zero_bit(context_asid_map, num_asids, 1); in __new_context() 140 __set_bit(asid, context_asid_map); in __new_context() 141 cur_idx = asid; in __new_context() 142 return asid | ver; in __new_context() [all …]
|
/openbmc/linux/arch/xtensa/include/asm/ |
H A D | mmu_context.h | 38 * NO_CONTEXT is the invalid ASID value that we don't ever assign to 72 unsigned long asid = cpu_asid_cache(cpu); in get_new_mmu_context() local 73 if ((++asid & ASID_MASK) == 0) { in get_new_mmu_context() 75 * Start new asid cycle; continue counting with next in get_new_mmu_context() 79 asid += ASID_USER_FIRST; in get_new_mmu_context() 81 cpu_asid_cache(cpu) = asid; in get_new_mmu_context() 82 mm->context.asid[cpu] = asid; in get_new_mmu_context() 89 * Check if our ASID is of an older version and thus invalid. in get_mmu_context() 93 unsigned long asid = mm->context.asid[cpu]; in get_mmu_context() local 95 if (asid == NO_CONTEXT || in get_mmu_context() [all …]
|
/openbmc/linux/arch/sh/mm/ |
H A D | tlbflush_32.c | 21 unsigned long asid; in local_flush_tlb_page() local 24 asid = cpu_asid(cpu, vma->vm_mm); in local_flush_tlb_page() 30 set_asid(asid); in local_flush_tlb_page() 32 local_flush_tlb_one(asid, page); in local_flush_tlb_page() 56 unsigned long asid; in local_flush_tlb_range() local 59 asid = cpu_asid(cpu, mm); in local_flush_tlb_range() 65 set_asid(asid); in local_flush_tlb_range() 68 local_flush_tlb_one(asid, start); in local_flush_tlb_range() 89 unsigned long asid; in local_flush_tlb_kernel_range() local 92 asid = cpu_asid(cpu, &init_mm); in local_flush_tlb_kernel_range() [all …]
|
/openbmc/linux/arch/sh/include/asm/ |
H A D | mmu_context_32.h | 6 static inline void set_asid(unsigned long asid) in set_asid() argument 8 __raw_writel(asid, MMU_PTEAEX); in set_asid() 16 static inline void set_asid(unsigned long asid) in set_asid() argument 25 : "r" (asid), "m" (__m(MMU_PTEH)), in set_asid() 31 unsigned long asid; in get_asid() local 34 : "=r" (asid) in get_asid() 36 asid &= MMU_CONTEXT_ASID_MASK; in get_asid() 37 return asid; in get_asid()
|
H A D | mmu_context.h | 6 * ASID handling idea taken from MIPS implementation. 22 * (b) ASID (Address Space IDentifier) 33 /* Impossible ASID value, to differentiate from NO_CONTEXT. */ 57 unsigned long asid = asid_cache(cpu); in get_mmu_context() local 60 if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0) in get_mmu_context() 65 if (!(++asid & MMU_CONTEXT_ASID_MASK)) { in get_mmu_context() 67 * We exhaust ASID of this version. in get_mmu_context() 76 if (!asid) in get_mmu_context() 77 asid = MMU_CONTEXT_FIRST_VERSION; in get_mmu_context() 80 cpu_context(cpu, mm) = asid_cache(cpu) = asid; in get_mmu_context() [all …]
|
/openbmc/linux/arch/csky/include/asm/ |
H A D | asid.h | 22 /* Number of ASID allocated by context (shift value) */ 37 * Check the ASID is still valid for the context. If not generate a new ASID. 39 * @pasid: Pointer to the current ASID batch 46 u64 asid, old_active_asid; in asid_check_context() local 48 asid = atomic64_read(pasid); in asid_check_context() 52 * If our active_asid is non-zero and the ASID matches the current in asid_check_context() 60 * - We get a valid ASID back from the cmpxchg, which means the in asid_check_context() 66 !((asid ^ atomic64_read(&info->generation)) >> info->bits) && in asid_check_context() 68 old_active_asid, asid)) in asid_check_context()
|
/openbmc/qemu/hw/arm/ |
H A D | trace-events | 14 smmu_iotlb_inv_asid_vmid(int asid, int vmid) "IOTLB invalidate asid=%d vmid=%d" 17 smmu_iotlb_inv_iova(int asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64 19 smmu_iotlb_lookup_hit(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "… 20 smmu_iotlb_lookup_miss(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) … 21 smmu_iotlb_insert(int asid, int vmid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d v… 50 …range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool l… 53 smmuv3_cmdq_tlbi_nh_asid(int asid) "asid=%d" 58 …ers_iova(const char *name, int asid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages, int …
|
H A D | smmu-common.c | 41 a += key->asid + key->vmid + key->level + key->tg; in smmu_iotlb_key_hash() 55 return (k1->asid == k2->asid) && (k1->iova == k2->iova) && in smmu_iotlb_key_equal() 60 SMMUIOTLBKey smmu_get_iotlb_key(int asid, int vmid, uint64_t iova, in smmu_get_iotlb_key() argument 63 SMMUIOTLBKey key = {.asid = asid, .vmid = vmid, .iova = iova, in smmu_get_iotlb_key() 85 key = smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, in smmu_iotlb_lookup_all_levels() 126 trace_smmu_iotlb_lookup_hit(cfg->asid, cfg->s2cfg.vmid, iova, in smmu_iotlb_lookup() 132 trace_smmu_iotlb_lookup_miss(cfg->asid, cfg->s2cfg.vmid, iova, in smmu_iotlb_lookup() 149 *key = smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, new->entry.iova, in smmu_iotlb_insert() 151 trace_smmu_iotlb_insert(cfg->asid, cfg->s2cfg.vmid, new->entry.iova, in smmu_iotlb_insert() 168 return (SMMU_IOTLB_ASID(*iotlb_key) == info->asid) && in smmu_hash_remove_by_asid_vmid() [all …]
|
/openbmc/linux/drivers/misc/sgi-gru/ |
H A D | grumain.c | 56 /*--------- ASID Management ------------------------------------------- 62 * asid in use ("x"s below). Set "limit" to this value. 70 * Each time MAX_ASID is reached, increment the asid generation. Since 73 * a context, the asid generation of the GTS asid is rechecked. If it 74 * doesn't match the current generation, a new asid will be assigned. 79 * All asid manipulation & context loading/unloading is protected by the 83 /* Hit the asid limit. Start over */ 93 static int gru_reset_asid_limit(struct gru_state *gru, int asid) in gru_reset_asid_limit() argument 97 gru_dbg(grudev, "gid %d, asid 0x%x\n", gru->gs_gid, asid); in gru_reset_asid_limit() 100 if (asid >= limit) in gru_reset_asid_limit() [all …]
|
H A D | grutlbpurge.c | 89 * the ASID invalidated. Invalidating an ASID causes a new ASID to be assigned 122 * - asid[maxgrus] array. ASIDs are assigned to a GRU when a context is 132 * asid is non-zero. 136 * - if the ctxtmap is zero, no context is active. Set the ASID to 150 int grupagesize, pagesize, pageshift, gid, asid; in gru_flush_tlb_range() local 167 asid = asids->mt_asid; in gru_flush_tlb_range() 168 if (asids->mt_ctxbitmap && asid) { in gru_flush_tlb_range() 170 asid = GRUASID(asid, start); in gru_flush_tlb_range() 172 " FLUSH gruid %d, asid 0x%x, vaddr 0x%lx, vamask 0x%x, num %ld, cbmap 0x%x\n", in gru_flush_tlb_range() 173 gid, asid, start, grupagesize, num, asids->mt_ctxbitmap); in gru_flush_tlb_range() [all …]
|
/openbmc/linux/drivers/accel/habanalabs/common/ |
H A D | asid.c | 20 /* ASID 0 is reserved for the kernel driver and device CPU */ in hl_asid_init() 50 void hl_asid_free(struct hl_device *hdev, unsigned long asid) in hl_asid_free() argument 52 if (asid == HL_KERNEL_ASID_ID || asid >= hdev->asic_prop.max_asid) { in hl_asid_free() 53 dev_crit(hdev->dev, "Invalid ASID %lu", asid); in hl_asid_free() 57 clear_bit(asid, hdev->asid_bitmap); in hl_asid_free()
|
/openbmc/linux/arch/x86/mm/ |
H A D | tlb.c | 63 * to what is traditionally called ASID on the RISC processors. 65 * We don't use the traditional ASID implementation, where each process/mm gets 66 * its own ASID and flush/restart when we run out of ASID space. 75 * ASID - [0, TLB_NR_DYN_ASIDS-1] 80 * ASID+1, because PCID 0 is special. 84 * PCID values, but we can still do with a single ASID denomination 112 * Given @asid, compute kPCID 114 static inline u16 kern_pcid(u16 asid) in kern_pcid() argument 116 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE); in kern_pcid() 120 * Make sure that the dynamic ASID space does not conflict with the in kern_pcid() [all …]
|
/openbmc/linux/arch/loongarch/include/asm/ |
H A D | mmu_context.h | 22 * as a software asid extension. 34 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 54 u64 asid = asid_cache(cpu); in get_new_mmu_context() local 56 if (!((++asid) & cpu_asid_mask(&cpu_data[cpu]))) in get_new_mmu_context() 57 local_flush_tlb_user(); /* start new asid cycle */ in get_new_mmu_context() 59 cpu_context(cpu, mm) = asid_cache(cpu) = asid; in get_new_mmu_context() 82 /* Check if our ASID is of an older version and thus invalid */ in switch_mm_irqs_off() 130 int asid; in drop_mmu_context() local 135 asid = read_csr_asid() & cpu_asid_mask(¤t_cpu_data); in drop_mmu_context() 137 if (asid == cpu_asid(cpu, mm)) { in drop_mmu_context()
|
/openbmc/linux/drivers/vhost/ |
H A D | vdpa.c | 70 u64 last, u32 asid); 79 static struct vhost_vdpa_as *asid_to_as(struct vhost_vdpa *v, u32 asid) in asid_to_as() argument 81 struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS]; in asid_to_as() 85 if (as->id == asid) in asid_to_as() 91 static struct vhost_iotlb *asid_to_iotlb(struct vhost_vdpa *v, u32 asid) in asid_to_iotlb() argument 93 struct vhost_vdpa_as *as = asid_to_as(v, asid); in asid_to_iotlb() 101 static struct vhost_vdpa_as *vhost_vdpa_alloc_as(struct vhost_vdpa *v, u32 asid) in vhost_vdpa_alloc_as() argument 103 struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS]; in vhost_vdpa_alloc_as() 106 if (asid_to_as(v, asid)) in vhost_vdpa_alloc_as() 109 if (asid >= v->vdpa->nas) in vhost_vdpa_alloc_as() [all …]
|
/openbmc/linux/arch/arm64/include/asm/ |
H A D | tlbflush.h | 58 #define __TLBI_VADDR(addr, asid) \ argument 62 __ta |= (unsigned long)(asid) << 48; \ 129 * | ASID | TG | SCALE | NUM | TTL | BADDR | 137 #define __TLBI_VADDR_RANGE(addr, asid, scale, num, ttl) \ argument 145 __ta |= (unsigned long)(asid) << 48; \ 192 * The 'mm' argument identifies the ASID to invalidate. 255 unsigned long asid; in flush_tlb_mm() local 258 asid = __TLBI_VADDR(0, ASID(mm)); in flush_tlb_mm() 259 __tlbi(aside1is, asid); in flush_tlb_mm() 260 __tlbi_user(aside1is, asid); in flush_tlb_mm() [all …]
|
/openbmc/linux/drivers/iommu/arm/arm-smmu-v3/ |
H A D | arm-smmu-v3-sva.c | 41 * Check if the CPU ASID is available on the SMMU side. If a private context 45 arm_smmu_share_asid(struct mm_struct *mm, u16 asid) in arm_smmu_share_asid() argument 53 cd = xa_load(&arm_smmu_asid_xa, asid); in arm_smmu_share_asid() 73 * Race with unmap: TLB invalidations will start targeting the new ASID, in arm_smmu_share_asid() 74 * which isn't assigned yet. We'll do an invalidate-all on the old ASID in arm_smmu_share_asid() 77 cd->asid = new_asid; in arm_smmu_share_asid() 79 * Update ASID and invalidate CD in all associated masters. There will in arm_smmu_share_asid() 86 arm_smmu_tlb_inv_asid(smmu, asid); in arm_smmu_share_asid() 88 xa_erase(&arm_smmu_asid_xa, asid); in arm_smmu_share_asid() 94 u16 asid; in arm_smmu_alloc_shared_cd() local [all …]
|
/openbmc/linux/tools/perf/pmu-events/arch/riscv/ |
H A D | riscv-sbi-firmware.json | 75 "PublicDescription": "Sent SFENCE.VMA with ASID request to other HART event", 78 "BriefDescription": "Sent SFENCE.VMA with ASID request to other HART event" 81 "PublicDescription": "Received SFENCE.VMA with ASID request from other HART event", 84 "BriefDescription": "Received SFENCE.VMA with ASID request from other HART event" 123 "PublicDescription": "Sent HFENCE.VVMA with ASID request to other HART event", 126 "BriefDescription": "Sent HFENCE.VVMA with ASID request to other HART event" 129 "PublicDescription": "Received HFENCE.VVMA with ASID request from other HART event", 132 "BriefDescription": "Received HFENCE.VVMA with ASID request from other HART event"
|
/openbmc/linux/drivers/iommu/arm/arm-smmu/ |
H A D | qcom_iommu.c | 54 struct qcom_iommu_ctx *ctxs[]; /* indexed by asid */ 62 u8 asid; /* asid and ctx bank # are 1:1 */ member 92 static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid) in to_ctx() argument 97 return qcom_iommu->ctxs[asid]; in to_ctx() 151 iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid); in qcom_iommu_tlb_inv_context() 171 iova |= ctx->asid; in qcom_iommu_tlb_inv_range_nosync() 217 fsr, iova, fsynr, ctx->asid); in qcom_iommu_fault() 268 ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid); in qcom_iommu_init_domain() 292 FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid)); in qcom_iommu_init_domain() 527 unsigned asid = args->args[0]; in qcom_iommu_of_xlate() local [all …]
|
/openbmc/linux/arch/riscv/kvm/ |
H A D | tlb.c | 78 unsigned long asid, in kvm_riscv_local_hfence_vvma_asid_gva() argument 86 kvm_riscv_local_hfence_vvma_asid_all(vmid, asid); in kvm_riscv_local_hfence_vvma_asid_gva() 96 : : "r" (pos), "r" (asid) : "memory"); in kvm_riscv_local_hfence_vvma_asid_gva() 101 : : "r" (pos), "r" (asid) : "memory"); in kvm_riscv_local_hfence_vvma_asid_gva() 108 unsigned long asid) in kvm_riscv_local_hfence_vvma_asid_all() argument 114 asm volatile(HFENCE_VVMA(zero, %0) : : "r" (asid) : "memory"); in kvm_riscv_local_hfence_vvma_asid_all() 269 READ_ONCE(v->vmid), d.asid, in kvm_riscv_hfence_process() 275 READ_ONCE(v->vmid), d.asid); in kvm_riscv_hfence_process() 340 data.asid = 0; in kvm_riscv_hfence_gvma_vmid_gpa() 358 unsigned long order, unsigned long asid) in kvm_riscv_hfence_vvma_asid_gva() argument [all …]
|
/openbmc/linux/arch/riscv/include/asm/ |
H A D | tlbflush.h | 25 static inline void local_flush_tlb_all_asid(unsigned long asid) in local_flush_tlb_all_asid() argument 27 if (asid != FLUSH_TLB_NO_ASID) in local_flush_tlb_all_asid() 28 ALT_SFENCE_VMA_ASID(asid); in local_flush_tlb_all_asid() 40 unsigned long asid) in local_flush_tlb_page_asid() argument 42 if (asid != FLUSH_TLB_NO_ASID) in local_flush_tlb_page_asid() 43 ALT_SFENCE_VMA_ADDR_ASID(addr, asid); in local_flush_tlb_page_asid()
|