| /openbmc/linux/arch/arm64/ |
| H A D | Kconfig.platforms | 1 # SPDX-License-Identifier: GPL-2.0-only
12 bool "Allwinner sunxi 64-bit SoC Family"
20 This enables support for Allwinner sunxi based SoCs like the A64.
33 This enables support for Apple's in-house ARM SoC family, starting
61 This enables support for Broadcom iProc based SoCs
67 Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
70 This enables support for Broadcom BCA ARM-based broadband chipsets,
74 bool "Broadcom Set-Top-Box SoCs"
79 This enables support for Broadcom's ARMv8 Set Top Box SoCs
108 This enables support for ARMv8 based Samsung Exynos SoC family.
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
260 ARM 64-bit (AArch64) Linux support.
269 depends on $(cc-option,-fpatchable-function-entry=2)
301 # VA_BITS - PAGE_SHIFT - 3
377 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
432 at stage-2.
440 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
445 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
448 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
454 data cache clean-and-invalidate.
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| /openbmc/linux/drivers/perf/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 Say y if you want to use CPU performance monitors on ARM-based
61 bool "RISC-V PMU framework"
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| /openbmc/openbmc/meta-raspberrypi/docs/ |
| H A D | layer-contents.md | 7 * raspberrypi0-wifi
8 * raspberrypi0-2w-64
11 * raspberrypi3-64 (64 bit kernel & userspace)
13 * raspberrypi4-64 (64 bit kernel & userspace)
14 * raspberrypi-cm (dummy alias for raspberrypi)
15 * raspberrypi-cm3
19 ## Multi-board Machines
29 ### raspberrypi-armv7
31 This machine targets support for all the ARMv7-based Raspberry Pi boards. It
35 ### raspberrypi-armv8
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| /openbmc/linux/Documentation/trace/coresight/ |
| H A D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
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| /openbmc/openbmc/meta-raspberrypi/dynamic-layers/multimedia-layer/recipes-multimedia/libcamera-apps/ |
| H A D | libcamera-apps_git.bb | 1 SUMMARY = "A suite of libcamera-based apps"
2 DESCRIPTION = "This is a small suite of libcamera-based apps that aim to \
4 HOMEPAGE = "https://github.com/raspberrypi/libcamera-apps"
7 LICENSE = "BSD-2-Clause"
11 git://github.com/raspberrypi/libcamera-apps.git;protocol=https;branch=main \
12 file://0001-utils-version.py-use-usr-bin-env-in-shebang.patch \
13 file://0002-Revert-Support-compressed-pixel-formats-when-saving-.patch \
23 PACKAGECONFIG[libav] = "-Denable_libav=true, -Denable_libav=false, libav"
24 PACKAGECONFIG[drm] = "-Denable_drm=true, -Denable_drm=false, libdrm"
25 PACKAGECONFIG[egl] = "-Denable_egl=true, -Denable_egl=false, virtual/egl"
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| /openbmc/linux/Documentation/virt/hyperv/ |
| H A D | clocks.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 -----
8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
14 per-CPU timers as described in the TLFS, they are not used by the
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead.
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| /openbmc/openbmc/poky/meta/recipes-devtools/valgrind/valgrind/ |
| H A D | 0001-makefiles-Drop-setting-mcpu-to-cortex-a8-on-arm-arch.patch | 3 Date: Thu, 20 Apr 2017 10:11:16 -0700
4 Subject: [PATCH] makefiles: Drop setting -mcpu to cortex-a8 on arm
7 We can not assume that all arches armv7+ are cortex-a8 only
8 it fails to build for rpi which is armv7ve based (cortex-a8) cpu
11 | cc1: warning: switch -mcpu=cortex-a8 conflicts with -march=armv7ve switch
13 Upstream-Status: Submitted [https://bugs.kde.org/show_bug.cgi?id=454346]
15 Signed-off-by: Khem Raj <raj.khem@gmail.com>
16 ---
17 Makefile.all.am | 6 +++---
18 helgrind/tests/Makefile.am | 6 +++---
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| /openbmc/u-boot/arch/arm/mach-rmobile/ |
| H A D | lowlevel_init_gen3.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S
8 * This file is based on the arch/arm/cpu/armv8/start.S
14 #include <asm-offsets.h>
24 * For single-entry systems the lowlevel init is very simple.
|
| /openbmc/linux/Documentation/devicetree/bindings/arm/nuvoton/ |
| H A D | nuvoton,ma35d1.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton MA35 series SoC based platforms
10 - Jacky Huang <ychuang3@nuvoton.com>
13 Boards with an ARMv8 based Nuvoton MA35 series SoC shall have
22 - description: MA35D1 based boards
24 - enum:
25 - nuvoton,ma35d1-iot
26 - nuvoton,ma35d1-som
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| /openbmc/u-boot/arch/arm/ |
| H A D | Kconfig | 14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
20 information that is embedded into the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
28 U-Boot typically uses a hard-coded value for the stack pointer
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that can be loaded and executed at arbitrary
41 Place a Linux kernel image header at the start of the U-Boot binary.
45 U-Boot needs to use, but which isn't part of the binary.
74 Do not enable instruction cache in U-Boot
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| /openbmc/linux/arch/arm64/crypto/ |
| H A D | polyval-ce-glue.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Glue code for POLYVAL using ARMv8 Crypto Extensions
5 * Copyright (c) 2007 Nokia Siemens Networks - Mikko Herranen <mh1@iki.fi>
12 * Glue code based on ghash-clmulni-intel_glue.c.
15 * ARMv8 Crypto Extensions instructions to implement the finite field operations.
56 polyval_update_non4k(keys->key_powers[NUM_KEY_POWERS-1], in, in internal_polyval_update()
79 return -EINVAL; in polyval_arm64_setkey()
81 memcpy(tctx->key_powers[NUM_KEY_POWERS-1], key, POLYVAL_BLOCK_SIZE); in polyval_arm64_setkey()
83 for (i = NUM_KEY_POWERS-2; i >= 0; i--) { in polyval_arm64_setkey()
84 memcpy(tctx->key_powers[i], key, POLYVAL_BLOCK_SIZE); in polyval_arm64_setkey()
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| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | microchip,sparx5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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| H A D | arm,coresight-cpu-debug.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight CPU debug component are compliant with the ARMv8 architecture
18 external debug module is mainly used for two modes: self-hosted debug and
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/libdeflate/ |
| H A D | libdeflate_1.20.bb | 1 SUMMARY = "libdeflate is a library for fast, whole-buffer DEFLATE-based compression and decompressi…
10 file://0001-lib-arm-don-t-use-explicit-armv8.2-a-on-gcc-13.2-and.patch \
|
| /openbmc/linux/drivers/soc/tegra/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
21 Support for NVIDIA Tegra AP20 and T20 processors, based on the
35 Support for NVIDIA Tegra T30 processor family, based on the
47 Support for NVIDIA Tegra T114 processor family, based on the
58 Support for NVIDIA Tegra T124 processor family, based on the
63 # 64-bit ARM SoCs
72 Enable support for NVIDIA Tegra132 SoC, based on the Denver
73 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
75 Tegra124's "4+1" Cortex-A15 CPU complex.
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| /openbmc/qemu/docs/system/arm/ |
| H A D | emulation.rst | 3 A-profile CPU architecture support
7 Armv8 and Armv9 versions of the A-profile architecture. It also has support for
10 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
11 - FEAT_AA32EL0 (Support for AArch32 at EL0)
12 - FEAT_AA32EL1 (Support for AArch32 at EL1)
13 - FEAT_AA32EL2 (Support for AArch32 at EL2)
14 - FEAT_AA32EL3 (Support for AArch32 at EL3)
15 - FEAT_AA32HPD (AArch32 hierarchical permission disables)
16 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
17 - FEAT_AA64EL0 (Support for AArch64 at EL0)
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| /openbmc/u-boot/doc/ |
| H A D | README.rmobile | 4 This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
5 and Cortex-A9/A53/A57 based R-Car[2] family of SoCs. Renesas's RMOBILE/R-Car SoC
6 family contains an ARM Cortex-A9/A53/A57.
12 | R8A73A0 | KMC KZM-A9-GT [3] | kzm9g_config
13 | R8A7734 | Atmark-Techno Armadillo-800-EVA [4] | armadillo-800eva_config
17 |---------------+----------------------------------------+-------------------
18 | R8A7791 M2-W | Renesas Electronics Koelsch | koelsch_defconfig
20 |---------------+----------------------------------------+-------------------
22 |---------------+----------------------------------------+-------------------
23 | R8A7793 M2-N | Renesas Electronics Gose | gose_defconfig
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| H A D | README.qemu-arm | 1 # SPDX-License-Identifier: GPL-2.0+
5 U-Boot on QEMU's 'virt' machine on ARM & AArch64
9 virtualization purposes. This document describes how to run U-Boot under it.
10 Both 32-bit ARM and AArch64 are supported.
14 - A freely configurable amount of CPU cores
15 - U-Boot loaded and executing in the emulated flash at address 0x0
16 - A generated device tree blob placed at the start of RAM
17 - A freely configurable amount of RAM, described by the DTB
18 - A PL011 serial port, discoverable via the DTB
19 - An ARMv7/ARMv8 architected timer
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| /openbmc/u-boot/arch/arm/mach-bcm283x/ |
| H A D | Kconfig | 17 bool "Broadcom BCM2837 SoC 32-bit support"
24 bool "Broadcom BCM2837 SoC 64-bit support"
39 Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as
41 support BCM2836/BCM2837-based Raspberry Pis such as the RPi 2 and
50 Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as
56 non-default option must be present in config.txt: enable_uart=1.
57 This is required for U-Boot to operate correctly, even if you only
66 Support for all BCM2836-based Raspberry Pi variants, such as
69 This option also supports BCM2837-based variants such as the RPi 3
70 Model B, when run in 32-bit mode, provided you have configured the
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| /openbmc/linux/Documentation/arch/arm64/ |
| H A D | memory-tagging-extension.rst | 8 Date: 2020-02-25
16 ARMv8.5 based processors introduce the Memory Tagging Extension (MTE)
17 feature. MTE is built on top of the ARMv8.0 virtual address tagging TBI
18 (Top Byte Ignore) feature and allows software to access a 4-bit
19 allocation tag for each 16-byte granule in the physical address space.
20 Such memory range must be mapped with the Normal-Tagged memory
21 attribute. A logical tag is derived from bits 59-56 of the virtual
34 --------
40 ``PROT_MTE`` - Pages allow access to the MTE allocation tags.
43 user address space and preserved on copy-on-write. ``MAP_SHARED`` is
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| /openbmc/linux/lib/ |
| H A D | Kconfig.kasan | 1 # SPDX-License-Identifier: GPL-2.0-only
23 def_bool $(cc-option, -fsanitize=kernel-address)
26 def_bool $(cc-option, -fsanitize=kernel-hwaddress)
43 Enables KASAN (Kernel Address Sanitizer) - a dynamic memory safety
44 error detector designed to find out-of-bounds and use-after-free bugs.
46 See Documentation/dev-tools/kasan.rst for details.
53 …def_bool (CC_IS_CLANG && $(cc-option,-fsanitize=kernel-address -mllvm -asan-kernel-mem-intrinsic-p…
54 (CC_IS_GCC && $(cc-option,-fsanitize=kernel-address --param asan-kernel-mem-intrinsic-prefix=1))
69 2. Software Tag-Based KASAN (arm64 only, based on software memory
72 3. Hardware Tag-Based KASAN (arm64 only, based on hardware memory
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| /openbmc/u-boot/board/qualcomm/dragonboard820c/ |
| H A D | u-boot.lds | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Override linker script for fastboot-readable images
7 * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
10 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
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| /openbmc/u-boot/board/qualcomm/dragonboard410c/ |
| H A D | u-boot.lds | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Override linker script for fastboot-readable images
7 * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
10 OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
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| /openbmc/qemu/tests/tcg/aarch64/ |
| H A D | mte-8.c | 2 * To be compiled with -march=armv8.5-a+memtag
6 … https://www.kernel.org/doc/html/next/arch/arm64/memory-tagging-extension.html#example-of-correct-…
57 * tag check faults (based on per-CPU preference) and allow all in main()
58 * non-zero tags in the randomly generated set. in main()
69 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); in main()
|