/openbmc/linux/Documentation/arch/arm/ |
H A D | microchip.rst | 7 ------------ 11 It is important to note that the Microchip (previously Atmel) ARM-based MPU 15 git branches/tags and email subject always contain this "at91" sub-string. 19 --------- 25 - at91rm9200 29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-1768-32-bit-ARM920T-Embedded-Microprocessor-… 32 - at91sam9260 36 …ttp://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6221-32-bit-ARM926EJ-S-Embedded-Microprocesso… 38 - at91sam9xe 42 …ttp://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocesso… [all …]
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/openbmc/linux/Documentation/devicetree/bindings/arm/ |
H A D | arm,versatile.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linus.walleij@linaro.org> 13 The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards 22 - description: The ARM Versatile Application Baseboard (HBI-0118) is an 23 evaluation board specifically for the ARM926EJ-S. It can be connected 24 to an IB1 interface board for a touchscreen-type use case or an IB2 25 for a candybar phone-type use case. See ARM DUI 0225D. 27 - const: arm,versatile-ab [all …]
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H A D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 59 On 32-bit ARM v7 or later systems this property is 68 On ARM v8 64-bit systems this property is required 71 * If cpus node's #address-cells property is set to 2 79 * If cpus node's #address-cells property is set to 1 [all …]
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/openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
H A D | at91_matrix.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 58 u32 reserve1[16 - AT91_MATRIX_MASTERS]; 60 u32 reserve2[16 - AT91_MATRIX_SLAVES]; 62 u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)]; 66 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */ 100 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 102 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 151 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 153 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 222 /* USB Pad Pull-Up Control Register */
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/openbmc/u-boot/board/armltd/integrator/ |
H A D | README | 2 U-Boot for ARM Integrator Development Platforms 8 Manuals available from :- 12 -------- 13 There are two Integrator variants - Integrator/AP and Integrator/CP. 24 ------------ 25 Integrator platforms can be configured to use U-Boot in at least three ways :- 26 a) Run ARM boot monitor, manually run U-Boot image from flash 27 b) Run ARM boot monitor, automatically run U-Boot image from flash 28 c) Run U-Boot image direct from flash. 32 U-Boot has to carry out minimal configration before standard code is run. [all …]
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/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | arm-realview-eb.dts | 23 /dts-v1/; 24 #include <dt-bindings/interrupt-controller/irq.h> 25 #include <dt-bindings/gpio/gpio.h> 26 #include "arm-realview-eb.dtsi" 30 compatible = "arm,realview-eb"; 35 * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache 39 * qemu-system-arm -M realview-eb 40 * Unless specified, QEMU will emulate an ARM926EJ-S core tile. 41 * Switches -cpu arm1136 or -cpu arm1176 emulates the other 45 #address-cells = <1>; [all …]
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H A D | integratorap.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 13 compatible = "arm,integrator-ap"; 16 #address-cells = <1>; 17 #size-cells = <0>; 27 /* compatible = "arm,arm926ej-s"; */ 30 * The documentation in ARM DUI 0138E page 3-12 states 32 * but painful trial-and-error has proved to me that it [all …]
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/openbmc/linux/arch/arm/mach-versatile/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 37 Support for ARM's Integrator platform. 52 bool "Include support for Integrator/IM-PD1" 60 The IM-PD1 is an add-on logic module for the Integrator which 62 The IM-PD1 can be found on the Integrator/PP2 platform. 77 bool "Integrator/CM922T-XA10 core module" 83 bool "Integrator/CM926EJ-S core module" 107 bool "Integrator/CM1026EJ-S core module" 113 bool "Integrator/CM1136JF-S core module" 129 bool "Integrator/CT926 (ARM926EJ-S) core tile" [all …]
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/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv5/ |
H A D | tune-arm926ejs.inc | 3 require conf/machine/include/arm/arch-armv5-dsp.inc 6 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'arm926ejs', ' -mcpu=arm926ej-s', '', d)}" 10 ARMPKGARCH:tune-arm926ejs = "arm926ejs" 12 TUNE_FEATURES:tune-arm926ejs = "arm thumb dsp arm926ejs" 13 PACKAGE_EXTRA_ARCHS:tune-arm926ejs = "${PACKAGE_EXTRA_ARCHS:tune-armv5te} arm926ejste arm926ejse"
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/openbmc/linux/arch/arm/mach-npcm/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 18 Winbond/Nuvoton WPCM450 BMC based on the ARM926EJ-S.
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/openbmc/linux/Documentation/arch/arm/vfp/ |
H A D | release-notes.rst | 11 on ARM926EJ-S. 13 This release has been validated against the SoftFloat-2b library by 14 John R. Hauser using the TestFloat-2a test suite. Details of this 21 - fdiv 22 - fsub 23 - fadd 24 - fmul 25 - fcmp 26 - fcmpe 27 - fcvtd [all …]
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/openbmc/linux/arch/arm/boot/dts/alphascale/ |
H A D | alphascale-asm9260.dtsi | 2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de> 7 #include <dt-bindings/clock/alphascale,asm9260.h> 10 #address-cells = <1>; 11 #size-cells = <1>; 12 interrupt-parent = <&icoll>; 20 #address-cells = <0>; 21 #size-cells = <0>; 24 compatible = "arm,arm926ej-s"; 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; [all …]
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/openbmc/linux/arch/arm/mm/ |
H A D | proc-arm926.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S 5 * Copyright (C) 1999-2001 ARM Limited 7 * hacked for non-paged-MM by Hyok S. Choi, 2003. 12 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt 19 #include <asm/pgtable-hwdef.h> 22 #include "proc-macros.S" 76 bic ip, ip, #0x1100 @ ...i...s........ 148 * - start - start address (inclusive) 149 * - end - end address (exclusive) [all …]
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/openbmc/linux/arch/arm/boot/dts/hisilicon/ |
H A D | sd5203.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 8 /dts-v1/; 13 interrupt-parent = <&vic>; 14 #address-cells = <1>; 15 #size-cells = <1>; 26 #address-cells = <1>; 27 #size-cells = <0>; 31 compatible = "arm,arm926ej-s"; 42 #address-cells = <1>; 43 #size-cells = <1>; [all …]
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/openbmc/qemu/hw/arm/ |
H A D | versatilepb.c | 4 * Copyright (c) 2005-2007 CodeSourcery. 24 #include "qemu/error-report.h" 29 #include "target/arm/cpu-qom.h" 63 static void vpb_sic_update(vpb_sic_state *s) in vpb_sic_update() argument 67 flags = s->level & s->mask; in vpb_sic_update() 68 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update() 71 static void vpb_sic_update_pic(vpb_sic_state *s) in vpb_sic_update_pic() argument 78 if (!(s->pic_enable & mask)) in vpb_sic_update_pic() 80 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic() 86 vpb_sic_state *s = (vpb_sic_state *)opaque; in vpb_sic_set_irq() local [all …]
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/openbmc/linux/arch/arm/boot/dts/st/ |
H A D | spear3xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 9 #address-cells = <1>; 10 #size-cells = <1>; 11 interrupt-parent = <&vic>; 14 #address-cells = <0>; 15 #size-cells = <0>; 18 compatible = "arm,arm926ej-s"; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 compatible = "simple-bus"; [all …]
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H A D | spear600.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 7 #address-cells = <1>; 8 #size-cells = <1>; 12 #address-cells = <0>; 13 #size-cells = <0>; 16 compatible = "arm,arm926ej-s"; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 compatible = "simple-bus"; 32 vic0: interrupt-controller@f1100000 { [all …]
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/openbmc/linux/arch/arm/boot/dts/vt8500/ |
H A D | vt8500.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * vt8500.dtsi - Device tree file for VIA VT8500 SoC 9 #address-cells = <1>; 10 #size-cells = <1>; 14 #address-cells = <0>; 15 #size-cells = <0>; 19 compatible = "arm,arm926ej-s"; 36 #address-cells = <1>; 37 #size-cells = <1>; 38 compatible = "simple-bus"; [all …]
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H A D | wm8650.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC 9 #address-cells = <1>; 10 #size-cells = <1>; 14 #address-cells = <0>; 15 #size-cells = <0>; 19 compatible = "arm,arm926ej-s"; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 compatible = "simple-bus"; [all …]
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H A D | wm8505.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC 9 #address-cells = <1>; 10 #size-cells = <1>; 14 #address-cells = <0>; 15 #size-cells = <0>; 19 compatible = "arm,arm926ej-s"; 38 #address-cells = <1>; 39 #size-cells = <1>; 40 compatible = "simple-bus"; [all …]
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/openbmc/qemu/docs/system/arm/ |
H A D | aspeed.rst | 1 …-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280… 6 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the 8 with dual cores ARM Cortex-A7 CPUs (1.2GHz) and more recently the AST2700 9 with quad cores ARM Cortex-A35 64 bits CPUs (1.6GHz) 16 - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC 17 - ``quanta-q71l-bmc`` OpenBMC Quanta BMC 18 - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S) 19 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176) 23 - ``ast2500-evb`` Aspeed AST2500 Evaluation board 24 - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC [all …]
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/openbmc/linux/arch/arm/boot/dts/nspire/ |
H A D | nspire.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&intc>; 12 #address-cells = <1>; 13 #size-cells = <0>; 16 compatible = "arm,arm926ej-s"; 27 compatible = "mmio-sram"; 29 #address-cells = <1>; 30 #size-cells = <1>; [all …]
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/openbmc/linux/arch/arm/boot/dts/nuvoton/ |
H A D | nuvoton-wpcm450.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 4 #include <dt-bindings/interrupt-controller/irq.h> 8 #address-cells = <1>; 9 #size-cells = <1>; 23 #address-cells = <1>; 24 #size-cells = <0>; 27 compatible = "arm,arm926ej-s"; 33 clk24m: clock-24mhz { 35 compatible = "fixed-clock"; 36 clock-frequency = <24000000>; [all …]
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/openbmc/linux/arch/arm/boot/dts/allwinner/ |
H A D | suniv-f1c100s.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR X11) 7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h> 8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h> 11 #address-cells = <1>; 12 #size-cells = <1>; 13 interrupt-parent = <&intc>; 16 osc24M: clk-24M { 17 #clock-cells = <0>; 18 compatible = "fixed-clock"; 19 clock-frequency = <24000000>; [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/lpc/ |
H A D | lpc32xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com> 9 #include <dt-bindings/clock/lpc32xx-clock.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 13 #address-cells = <1>; 14 #size-cells = <1>; 16 interrupt-parent = <&mic>; 19 #address-cells = <1>; 20 #size-cells = <0>; 23 compatible = "arm,arm926ej-s"; [all …]
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