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/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dahci-platform.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
13 It is possible, but not required, to represent each port as a sub-node.
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
23 compatible:
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H A Drockchip,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller found in Rockchip
19 compatible:
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
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H A Dsnps,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller.
18 compatible:
20 - snps,dwc-ahci
21 - snps,spear-ahci
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H A Dbrcm,sata-brcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SATA3 AHCI Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
14 - Florian Fainelli <f.fainelli@gmail.com>
17 - $ref: ahci-common.yaml#
20 compatible:
22 - items:
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H A Dnvidia,tegra-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra AHCI SATA Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 compatible:
16 - nvidia,tegra124-ahci
17 - nvidia,tegra132-ahci
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H A Dallwinner,sun8i-r40-ahci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner R40 AHCI SATA Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 compatible:
15 const: allwinner,sun8i-r40-ahci
22 - description: AHCI Bus Clock
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H A Dallwinner,sun4i-a10-ahci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/allwinner,sun4i-a10-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 AHCI SATA Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 compatible:
15 const: allwinner,sun4i-a10-ahci
22 - description: AHCI Bus Clock
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H A Dbaikal,bt1-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
20 compatible:
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H A Dahci-mtk.txt4 - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
5 When using "mediatek,mtk-ahci" compatible strings, you
7 - "mediatek,mt7622-ahci"
8 - reg : Physical base addresses and length of register sets.
9 - interrupts : Interrupt associated with the SATA device.
10 - interrupt-names : Associated name must be: "hostc".
11 - clocks : A list of phandle and clock specifier pairs, one for each
12 entry in clock-names.
13 - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
14 - phys : A phandle and PHY specifier pair for the PHY port.
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H A Dqcom-sata.txt1 * Qualcomm AHCI SATA Controller
3 SATA nodes are defined to describe on-chip Serial ATA controllers.
7 - compatible : compatible list, must contain "generic-ahci"
8 - interrupts : <interrupt mapping for SATA IRQ>
9 - reg : <registers mapping>
10 - phys : Must contain exactly one entry as specified
11 in phy-bindings.txt
12 - phy-names : Must be "sata-phy"
14 Required properties for "qcom,ipq806x-ahci" compatible:
15 - clocks : Must contain an entry for each entry in clock-names.
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H A Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX AHCI SATA Controller
10 - Shawn Guo <shawn.guo@linaro.org>
13 The Freescale i.MX SATA controller mostly conforms to the AHCI interface
17 compatible:
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
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H A Dahci-fsl-qoriq.txt1 Binding for Freescale QorIQ AHCI SATA Controller
4 - reg: Physical base address and size of the controller's register area.
5 - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
7 - clocks: Input clock specifier. Refer to common clock bindings.
8 - interrupts: Interrupt specifier. Refer to interrupt binding.
11 - dma-coherent: Enable AHCI coherent DMA operation.
12 - reg-names: register area names when there are more than 1 register area.
16 compatible = "fsl,ls1021a-ahci";
20 dma-coherent;
H A Dahci-da850.txt1 Device tree binding for the TI DA850 AHCI SATA Controller
2 ---------------------------------------------------------
5 - compatible: must be "ti,da850-ahci"
6 - reg: physical base addresses and sizes of the two register regions
8 AHCI 1.1 standard and the Power Down Control Register (PWRDN)
10 - interrupts: interrupt specifier (refer to the interrupt binding)
15 compatible = "ti,da850-ahci";
H A Dapm-xgene.txt1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
19 - interrupts : Interrupt-specifier for SATA host controller IRQ.
20 - clocks : Reference to the clock entry.
21 - phys : A list of phandles + phy-specifiers, one for each
22 entry in phy-names.
23 - phy-names : Should contain:
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H A Dahci-dm816.txt1 Device tree binding for the TI DM816 AHCI SATA Controller
2 ---------------------------------------------------------
5 - compatible: must be "ti,dm816-ahci"
6 - reg: physical base address and size of the register region used by
7 the controller (as defined by the AHCI 1.1 standard)
8 - interrupts: interrupt specifier (refer to the interrupt binding)
9 - clocks: list of phandle and clock specifier pairs (or only
11 #clock-cells); two clocks must be specified: the functional
17 compatible = "ti,dm816-ahci";
/openbmc/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-ahci-glue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC AHCI glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
14 logic handling signals to AHCI host controller inside AHCI component.
17 compatible:
19 - enum:
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dsocionext,uniphier-ahci-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-ahci-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier AHCI PHY
11 AHCI controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17 compatible:
19 - socionext,uniphier-pro4-ahci-phy
20 - socionext,uniphier-pxs2-ahci-phy
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/openbmc/linux/drivers/ata/
H A Dahci_platform.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AHCI SATA platform driver
5 * Copyright 2004-2005 Red Hat, Inc.
21 #include "ahci.h"
23 #define DRV_NAME "ahci"
45 struct device *dev = &pdev->dev; in ahci_probe()
59 if (device_is_compatible(dev, "hisilicon,hisi-ahci")) in ahci_probe()
60 hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ; in ahci_probe()
81 { .compatible = "generic-ahci", },
83 { .compatible = "ibm,476gtr-ahci", },
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H A Dahci_qoriq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale QorIQ AHCI SATA platform driver
18 #include "ahci.h"
20 #define DRV_NAME "ahci-qoriq"
70 { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
71 { .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
72 { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
73 { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
74 { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
75 { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
[all …]
/openbmc/u-boot/drivers/ata/
H A Dsata_ceva.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 - 2016 Xilinx, Inc.
8 #include <ahci.h>
71 #define DRV_NAME "ahci-ceva"
95 /* ecc addr-val pair */
119 ulong base = priv->base; in ceva_init_sata()
122 switch (priv->soc) { in ceva_init_sata()
142 if (priv->flag & FLAG_COHERENT) in ceva_init_sata()
154 if (priv->flag & FLAG_COHERENT) in ceva_init_sata()
162 if (priv->flag & FLAG_COHERENT) in ceva_init_sata()
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H A Dahci_mvebu.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <ahci.h>
36 * Board specific SATA / AHCI enable code, e.g. enable the in mvebu_ahci_probe()
37 * AHCI power or deassert reset in mvebu_ahci_probe()
47 { .compatible = "marvell,armada-3700-ahci" },
48 { .compatible = "marvell,armada-8k-ahci" },
/openbmc/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dakebono.txt11 - model : "ibm,akebono".
12 - compatible : "ibm,akebono" , "ibm,476gtr".
20 - compatible : should be "ibm,476gtr-sdhci","generic-sdhci".
21 - reg : should contain the SDHCI registers location and length.
22 - interrupts : should contain the SDHCI interrupt.
24 1.b) The Advanced Host Controller Interface (AHCI) SATA node
30 - compatible : should be "ibm,476gtr-ahci".
31 - reg : should contain the AHCI registers location and length.
32 - interrupts : should contain the AHCI interrupt.
41 - compatible : should be "ibm,akebono-fpga".
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/openbmc/u-boot/doc/device-tree-bindings/ata/
H A Dintel-sata.txt8 - compatible = "intel,pantherpoint-ahci"
9 - intel,sata-mode : string, one of:
10 "ahci" : Use AHCI mode (default)
12 "plain-ide" : Use plain IDE mode
13 - intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port,
15 - intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register
16 - intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register
19 -------
22 compatible = "intel,pantherpoint-ahci";
23 intel,sata-mode = "ahci";
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/openbmc/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dsata-uctl.txt4 and the SATA AHCI host controller (UAHC). It performs the following functions:
5 - provides interfaces for the applications to access the UAHC AHCI
7 - provides a bridge for UAHC to fetch AHCI command table entries and data
9 - posts interrupts to the CIU.
10 - contains registers that:
11 - control the behavior of the UAHC
12 - control the clock/reset generation to UAHC
13 - control endian swapping for all UAHC registers and DMA accesses
17 - compatible: "cavium,octeon-7130-sata-uctl"
21 - reg: The base address of the UCTL register bank.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dsocionext,uniphier-glue-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 compatible:
21 - socionext,uniphier-pro4-usb3-reset
22 - socionext,uniphier-pro5-usb3-reset
23 - socionext,uniphier-pxs2-usb3-reset
24 - socionext,uniphier-ld20-usb3-reset
[all …]

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