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/openbmc/qemu/target/arm/tcg/
H A Dtranslate-a32.h107 TCGv_i32 a32, int index, MemOp opc);
109 TCGv_i32 a32, int index, MemOp opc);
111 TCGv_i32 a32, int index, MemOp opc);
113 TCGv_i32 a32, int index, MemOp opc);
114 void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
116 void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
118 void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
120 void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
125 TCGv_i32 a32, int index) \
127 gen_aa32_ld_i32(s, val, a32, index, OPC); \
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H A Dneon-ls.decode23 # is a simple transformation of the A32 encoding.
24 # More specifically, this file covers instructions where the A32 encoding is
28 # This file works on the A32 encoding only; calling code for T32 has to
29 # transform the insn into the A32 version first.
H A Dmeson.build16 decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'),
17 decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
H A Da32-uncond.decode1 # A32 unconditional instructions
22 # All of those that have a COND field in insn[31:28] are in a32.decode
H A Dtranslate.c24 #include "translate-a32.h"
224 /* Return the core mmu_idx to use for A32/T32 "unprivileged load/store" in get_a32_user_mem_index()
920 static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) in gen_aa32_addr() argument
923 tcg_gen_extu_i32_tl(addr, a32); in gen_aa32_addr()
937 TCGv_i32 a32, int index, MemOp opc) in gen_aa32_ld_internal_i32() argument
939 TCGv addr = gen_aa32_addr(s, a32, opc); in gen_aa32_ld_internal_i32()
944 TCGv_i32 a32, int index, MemOp opc) in gen_aa32_st_internal_i32() argument
946 TCGv addr = gen_aa32_addr(s, a32, opc); in gen_aa32_st_internal_i32()
951 TCGv_i32 a32, int index, MemOp opc) in gen_aa32_ld_internal_i64() argument
953 TCGv addr = gen_aa32_addr(s, a32, opc); in gen_aa32_ld_internal_i64()
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H A Dvfp-uncond.decode22 # generally anything matching A32
H A Dneon-shared.decode23 # both A32 and T32.
/openbmc/linux/arch/x86/boot/
H A Dcpucheck.c57 #define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a)) macro
61 return cpu_vendor[0] == A32('A', 'u', 't', 'h') && in is_amd()
62 cpu_vendor[1] == A32('e', 'n', 't', 'i') && in is_amd()
63 cpu_vendor[2] == A32('c', 'A', 'M', 'D'); in is_amd()
68 return cpu_vendor[0] == A32('C', 'e', 'n', 't') && in is_centaur()
69 cpu_vendor[1] == A32('a', 'u', 'r', 'H') && in is_centaur()
70 cpu_vendor[2] == A32('a', 'u', 'l', 's'); in is_centaur()
75 return cpu_vendor[0] == A32('G', 'e', 'n', 'u') && in is_transmeta()
76 cpu_vendor[1] == A32('i', 'n', 'e', 'T') && in is_transmeta()
77 cpu_vendor[2] == A32('M', 'x', '8', '6'); in is_transmeta()
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/openbmc/qemu/tests/tcg/s390x/
H A Dadd-logical-with-carry.c44 unsigned int a32 = a, b32 = b, c32 = c; in test32rm() local
50 : [a] "+&r" (a32), [cc] "+&r" (*cc) in test32rm()
55 return (int)a32; in test32rm()
62 unsigned int a32 = a, b32 = b, c32 = c; in test32mr() local
68 : [a] "+&r" (a32), [c] "+&r" (c32), [cc] "+&r" (*cc) in test32mr()
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8a/
H A Dtune-cortexa32.inc3 TUNEVALID[cortexa32] = "Enable Cortex-A32 specific processor optimizations"
4 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa32', ' -mcpu=cortex-a32', '', d)}"
/openbmc/linux/tools/testing/selftests/rseq/
H A Drseq-arm.h11 * RSEQ_SIG uses the udf A32 instruction with an uncommon immediate operand
16 * The instruction pattern in the A32 instruction set is:
35 * Translates to this A32 instruction pattern:
/openbmc/qemu/tests/tcg/arm/
H A DMakefile.target39 ARM_TESTS += pcalign-a32
40 pcalign-a32: CFLAGS+=-marm
/openbmc/linux/arch/arm/include/asm/
H A Darch_gicv3.h41 #define CPUIF_MAP(a32, a64) \ argument
44 write_sysreg(val, a32); \
48 return read_sysreg(a32); \
/openbmc/linux/drivers/scsi/be2iscsi/
H A Dbe_mgmt.h145 bus_address.u.a32.address_lo; \
147 bus_address.u.a32.address_hi; \
H A Dbe_main.c1538 phys_addr.u.a32.address_lo = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, in beiscsi_hdl_get_handle()
1540 phys_addr.u.a32.address_lo -= dpl; in beiscsi_hdl_get_handle()
1541 phys_addr.u.a32.address_hi = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, in beiscsi_hdl_get_handle()
1761 pasync_sge[pi].hi = pasync_handle->pa.u.a32.address_lo; in beiscsi_hdq_post_handles()
1762 pasync_sge[pi].lo = pasync_handle->pa.u.a32.address_hi; in beiscsi_hdq_post_handles()
2101 io_task->bhs_pa.u.a32.address_lo); in hwi_write_sgl_v2()
2103 io_task->bhs_pa.u.a32.address_hi); in hwi_write_sgl_v2()
2143 io_task->bhs_pa.u.a32.address_hi); in hwi_write_sgl_v2()
2145 io_task->bhs_pa.u.a32.address_lo); in hwi_write_sgl_v2()
2196 io_task->bhs_pa.u.a32.address_lo); in hwi_write_sgl()
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/openbmc/libcper/include/libcper/sections/
H A Dcper-section-generic.h29 "IA32", "IA64", "X64", "ARM A32/T32", "ARM A64" \
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,corstone1000.yaml18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
H A Dpmu.yaml38 - arm,cortex-a32-pmu
/openbmc/qemu/target/arm/
H A Dcommon-semi-target.h56 /* Ok for A64, invalid for A32/T32 */ in common_semi_has_synccache()
/openbmc/linux/arch/arm/kernel/
H A Dopcodes.c5 * A32 condition code lookup feature moved from nwfpe/fpopcode.c
/openbmc/linux/include/linux/
H A Detherdevice.h581 u32 *a32 = (u32 *)((u8 *)a + 2); in compare_ether_header()
584 return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) | in compare_ether_header()
585 (a32[1] ^ b32[1]) | (a32[2] ^ b32[2]); in compare_ether_header()
/openbmc/linux/drivers/net/ethernet/brocade/bna/
H A Dbfa_ioc.h55 dma_addr->a32.addr_lo = (u32) htonl(pa); in __bfa_dma_be_addr_set()
56 dma_addr->a32.addr_hi = (u32) htonl(upper_32_bits(pa)); in __bfa_dma_be_addr_set()
/openbmc/qemu/linux-user/arm/
H A Dvdso.S16 * is useful for testing gcc, which requires we avoid A32 instructions.
/openbmc/u-boot/arch/x86/cpu/
H A Dstart16.S16 #define a32 .byte 0x67; macro
/openbmc/linux/drivers/staging/vme_user/
H A Dvme_tsi148.h681 #define TSI148_LCSR_OTAT_AMODE_A32 (2<<0) /* A32 Address Space */
682 #define TSI148_LCSR_OTAT_AMODE_A64 (4<<0) /* A32 Address Space */
877 #define TSI148_LCSR_ITAT_AS_A32 (2<<4) /* A32 Address Space */
950 #define TSI148_LCSR_LMAT_AS_A32 (2<<4) /* A32 */
1292 #define TSI148_LCSR_DSAT_AMODE_A32 (2<<0) /* A32 */
1329 #define TSI148_LCSR_DDAT_AMODE_A32 (2<<0) /* A32 */

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