/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | apm-xgene-phy.txt | 1 * APM X-Gene 15Gbps Multi-purpose PHY nodes 3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each 48 0 = 1-2Gbps 49 1 = 2-4Gbps (1st tuple default) 50 2 = 4-8Gbps 51 3 = 8-15Gbps (2nd tuple default) 52 4 = 2.5-4Gbps 53 5 = 4-5Gbps 54 6 = 5-6Gbps 55 7 = 6-16Gbps (3rd tuple default)
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/openbmc/linux/drivers/scsi/mvsas/ |
H A D | mv_94xx.h | 147 MVS_IRQ_COM_OUT_I2O_HOS2 = (1 << 6), 180 * bit 2: 6Gbps support 181 * bit 1: 3Gbps support 182 * bit 0: 1.5Gbps support 188 * bit 5: G1 (1.5Gbps) Without SSC 189 * bit 4: G1 (1.5Gbps) with SSC 190 * bit 3: G2 (3.0Gbps) Without SSC 191 * bit 2: G2 (3.0Gbps) with SSC 192 * bit 1: G3 (6.0Gbps) without SSC 193 * bit 0: G3 (6.0Gbps) with SSC [all …]
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
H A D | README.soc | 8 6. LS2088A 101 - Cryptography acceleration (SEC) at up to 10 Gbps 102 - RegEx pattern matching acceleration (PME) at up to 10 Gbps 103 - Decompression/compression acceleration (DCE) at up to 20 Gbps 104 - Accelerated I/O processing (AIOP) at up to 20 Gbps 108 - Up to eight 10 Gbps Ethernet MACs 109 - Up to eight 1 / 2.5 Gbps Ethernet MACs 144 Support for up to 6 GBaud operation 192 - Up to 1 x QSGMII (MAC 5, 6, 10, 1) 193 - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) [all …]
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/openbmc/u-boot/drivers/phy/marvell/ |
H A D | comphy_core.c | 23 "1.25 Gbps", "1.5 Gbps", "2.5 Gbps", in get_speed_string() 24 "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps", in get_speed_string() 25 "6.25 Gbps", "10.31 Gbps" in get_speed_string()
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H A D | comphy_a3700.c | 66 /* 0 1 2 3 4 5 6 7 */ 197 * 6. Enable the output of 100M/125M/500M clock in comphy_pcie_power_up() 440 * 6. Enable the output of 500M clock in comphy_usb3_power_up() 465 * 10. Set max speed generation to USB3.0 5Gbps in comphy_usb3_power_up() 672 * All PHY register values are defined in full for 3.125Gbps in comphy_sgmii_phy_init() 673 * SERDES speed. The values required for 1.25 Gbps are almost in comphy_sgmii_phy_init() 675 * comparison to 3.125 Gbps values. These register values are in comphy_sgmii_phy_init() 780 * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps in comphy_sgmii_power_up()
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/openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
H A D | maxim,max96712.yaml | 21 Each GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the 23 MAX96712 can be paired with first-generation 3.12Gbps or 1.5Gbps GMSL1 24 serializers or operate up to 3.12Gbps with GMSL2 serializers in GMSL1 mode.
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_dp_types.h | 50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2) - 3.24 Gbps/Lane 55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2) - 5.40 Gbps/Lane 57 LINK_RATE_RATE_8 = 0x19, // Rate_8 - 6.75 Gbps/Lane 58 LINK_RATE_HIGH3 = 0x1E, // Rate_9 (HBR3) - 8.10 Gbps/Lane 62 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane [all …]
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/openbmc/linux/drivers/net/ethernet/ezchip/ |
H A D | nps_enet.h | 59 /* Gbps Eth MAC Configuration 0 register masks and shifts */ 73 #define CFG_0_RX_CRC_STRIP_SHIFT 6 93 /* Gbps Eth MAC Configuration 1 register masks and shifts */ 103 /* Gbps Eth MAC Configuration 2 register masks and shifts */ 119 /* Gbps Eth MAC Configuration 3 register masks and shifts */ 131 #define CFG_3_CF_TIMEOUT_SHIFT 6
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/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
H A D | smu11_driver_if_arcturus.h | 62 #define FEATURE_DPM_XGMI_BIT 6 193 #define THROTTLER_TEMP_VR_SOC_BIT 6 429 XGMI_LINK_RATE_2 = 2, // 2Gbps 430 XGMI_LINK_RATE_4 = 4, // 4Gbps 431 XGMI_LINK_RATE_8 = 8, // 8Gbps 432 XGMI_LINK_RATE_12 = 12, // 12Gbps 433 XGMI_LINK_RATE_16 = 16, // 16Gbps 434 XGMI_LINK_RATE_17 = 17, // 17Gbps 435 XGMI_LINK_RATE_18 = 18, // 18Gbps 436 XGMI_LINK_RATE_19 = 19, // 19Gbps [all …]
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H A D | smu11_driver_if_sienna_cichlid.h | 51 #define NUM_OD_FAN_MAX_POINTS 6 82 #define FEATURE_DPM_MP0CLK_BIT 6 201 #define THROTTLER_TEMP_VR_MEM1_BIT 6 225 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6 524 XGMI_LINK_RATE_2 = 2, // 2Gbps 525 XGMI_LINK_RATE_4 = 4, // 4Gbps 526 XGMI_LINK_RATE_8 = 8, // 8Gbps 527 XGMI_LINK_RATE_12 = 12, // 12Gbps 528 XGMI_LINK_RATE_16 = 16, // 16Gbps 529 XGMI_LINK_RATE_17 = 17, // 17Gbps [all …]
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/openbmc/u-boot/board/freescale/t208xqds/ |
H A D | README | 19 - Up to four 10 Gbps Ethernet MACs 20 - Up to eight 1 Gbps Ethernet MACs 21 - Up to four 2.5 Gbps Ethernet MACs 40 1G Ethernet numbers: 8 6 57 - Two 1Gbps RGMII on-board ports 58 - Four 10Gbps XFI on-board cages 59 - 1Gbps/2.5Gbps SGMII Riser card 60 - 10Gbps XAUI Riser card 114 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a 118 hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
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/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/ |
H A D | qos_ets_strict.sh | 24 # | >1Gbps | | >1Gbps | 33 # | | 1Gbps bottleneck | 53 NUM_NETIFS=6 119 lldptool -T -i $swp3 -V ETS-CFG up2tc=0:0,1:1,2:2,3:3,4:4,5:5,6:6,7:7 127 )"6:strict,"$( 161 devlink_port_pool_th_set $swp1 0 6 163 devlink_tc_bind_pool_th_set $swp1 1 ingress 0 6 166 devlink_port_pool_th_set $swp2 0 6 168 devlink_tc_bind_pool_th_set $swp2 2 ingress 0 6 204 lldptool -T -i $swp3 -V ETS-CFG up2tc=0:0,1:0,2:0,3:0,4:0,5:0,6:0,7:0
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H A D | qos_mc_aware.sh | 39 # | >1Gbps | | >1Gbps | 48 # | | 1Gbps bottleneck | 68 NUM_NETIFS=6 267 # degradation on 1Gbps link.
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H A D | qos_pfc.sh | 43 # | | 1Gbps | | 1Gbps | 79 NUM_NETIFS=6 134 devlink_pool_size_thtype_save 6 137 devlink_port_pool_th_save $swp2 6 159 devlink_pool_size_thtype_set 6 static $_10MB 175 ets bands 8 strict 8 priomap 7 6 186 devlink_port_pool_th_set $swp2 6 $_10MB 187 devlink_tc_bind_pool_th_set $swp2 1 egress 6 $_10MB 189 # prio 0->TC0 (band 7), 1->TC1 (band 6). TC1 is shaped. 191 ets bands 8 strict 8 priomap 7 6 [all …]
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/openbmc/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_cx0_phy.c | 61 * It is required that PSR and DC5/6 are disabled before any CX0 message 352 return 6; in intel_c10_get_tx_term_ctl() 436 .pll[6] = 0x98, 462 .pll[6] = 0x75, 488 .pll[6] = 0xE3, 514 .pll[6] = 0x29, 540 .pll[6] = 0x98, 566 .pll[6] = 0x75, 592 .pll[6] = 0x29, 618 .pll[6] = 0x33, [all …]
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/openbmc/linux/include/rdma/ |
H A D | opa_port_info.h | 33 #define OPA_LINKDOWN_REASON_BAD_DLID 6 96 #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */ 97 #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */ 98 #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */ 107 #define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6) 216 OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6), 242 u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */
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/openbmc/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
H A D | hclge_main.h | 114 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 116 #define HCLGE_PHY_MDIX_STATUS_B 6 158 #define HCLGE_VECTOR0_CORERESET_INT_B 6 169 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U 192 #define HCLGE_SUPPORT_100M_BIT BIT(6) 235 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 236 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 237 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 238 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 239 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ [all …]
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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/ |
H A D | high_speed_env_spec.h | 59 * SGMII 1.25 Gbps 3.125 Gbps 74 {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
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/openbmc/linux/arch/arm64/boot/dts/marvell/ |
H A D | armada-8040-puzzle-m801.dts | 97 gpios = <&cp1_gpio1 6 GPIO_ACTIVE_LOW>; 108 /* SFP+ port 2: 10 Gbps indicator */ 115 /* SFP+ port 2: 1 Gbps indicator */ 122 /* SFP+ port 1: 10 Gbps indicator */ 129 /* SFP+ port 1: 1 Gbps indicator */ 135 led-6 {
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/openbmc/u-boot/board/freescale/t208xrdb/ |
H A D | README | 19 - Up to four 10 Gbps Ethernet MACs 20 - Up to eight 1 Gbps Ethernet MACs 21 - Up to four 2.5 Gbps Ethernet MACs 40 1G Ethernet numbers: 8 6 60 - Two on-board 10Gbps XFI fiber ports 61 - Two on-board 10Gbps Base-T copper ports
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/openbmc/qemu/docs/ |
H A D | rdma.txt | 107 Using a 40gbps infiniband link performing a worst-case stress test, 120 active use and the VM itself is completely idle using the same 40 gbps 123 1. rdma-pin-all disabled total time: approximately 7.5 seconds @ 9.5 Gbps 124 2. rdma-pin-all enabled total time: approximately 4 seconds @ 26 Gbps 183 6. Check versioning and capabilities (described later) 211 6. RAM Blocks result (used right after connection setup) 223 After connection setup, message 5 & 6 are used to exchange ram block 258 'Register result' commands #6 back to the sender which
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/openbmc/linux/drivers/usb/host/ |
H A D | xhci-hub.c | 25 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */ 26 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */ 27 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */ 28 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */ 29 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */ 30 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */ 31 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */ 32 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */ 169 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */ in xhci_create_usb3x_bos_desc() 186 * is 20Gbps, but the BOS descriptor lane speed mantissa is in xhci_create_usb3x_bos_desc() [all …]
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/openbmc/linux/drivers/net/phy/ |
H A D | realtek.c | 65 #define RTL_LPADV_5000FULL BIT(6) 989 .name = "RTL8226 2.5Gbps PHY", 1002 .name = "RTL8226B_RTL8221B 2.5Gbps PHY", 1014 .name = "RTL8226-CG 2.5Gbps PHY", 1024 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY", 1034 .name = "RTL8221B-VB-CG 2.5Gbps PHY", 1044 .name = "RTL8221B-VM-CG 2.5Gbps PHY",
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/openbmc/u-boot/board/freescale/ls1021atwr/ |
H A D | README | 16 performance of over 6,000, as well as virtualization support, advanced 43 - 4-lane 6GHz SerDes 46 - One Serial ATA 3.0 supporting 6 GT/s operation 65 - IPSec forwarding at up to 1Gbps
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/openbmc/linux/drivers/phy/mediatek/ |
H A D | phy-mtk-hdmi-mt8195.c | 33 /* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G, in mtk_phy_tmds_clk_ratio() 34 * clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10 in mtk_phy_tmds_clk_ratio() 121 case 6: in mtk_hdmi_pll_set_hw() 170 case 6: in mtk_hdmi_pll_set_hw() 214 u8 txpredivs[4] = { 2, 4, 6, 12 }; in mtk_hdmi_pll_calc() 249 /* calculate txprediv: can be 2, 4, 6, 12 in mtk_hdmi_pll_calc() 312 * 3G < data rate <= 6G: enable impedance 100ohm, in mtk_hdmi_pll_drv_setting() 321 /* 3G < data rate <= 6G, 300M < tmds rate <= 594M */ in mtk_hdmi_pll_drv_setting()
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