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Searched +full:5 +full:vs2 (Results 1 – 15 of 15) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dvcrypto_helper.c218 void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
229 round_key.d[0] = *((uint64_t *)vs2 + H8(i * 2 + 0)); \
230 round_key.d[1] = *((uint64_t *)vs2 + H8(i * 2 + 1)); \
244 void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
255 round_key.d[0] = *((uint64_t *)vs2 + H8(0)); \
256 round_key.d[1] = *((uint64_t *)vs2 + H8(1)); \
307 uint32_t *vs2 = vs2_vptr; local
326 rk[0] = vs2[i * 4 + H4(0)];
327 rk[1] = vs2[i * 4 + H4(1)];
328 rk[2] = vs2[i * 4 + H4(2)];
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H A Dvector_helper.c508 uint32_t idx, void *vs2);
512 uint32_t idx, void *vs2) \
514 return (base + *((ETYPE *)vs2 + H(idx))); \
524 void *vs2, CPURISCVState *env, uint32_t desc, in GEN_VEXT_GET_INDEX_ADDR()
549 abi_ptr addr = get_index_addr(base, i, vs2) + (k << log2_esz); in GEN_VEXT_GET_INDEX_ADDR()
561 void *vs2, CPURISCVState *env, uint32_t desc) \
563 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
586 void *vs2, CPURISCVState *env, uint32_t desc) \ in GEN_VEXT_LD_INDEX()
588 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ in GEN_VEXT_LD_INDEX()
1085 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ in RVVCALL()
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/openbmc/linux/drivers/pcmcia/
H A Dbcm63xx_pcmcia.c111 * identity cardtype from VS[12] input, CD[12] input while only VS2 is
120 IN_CD2_VS1H = (1 << 5),
125 /* VS1 float, VS2 float */
128 /* VS1 grounded, VS2 float */
131 /* VS1 grounded, VS2 grounded */
134 /* VS1 tied to CD1, VS2 float */
137 /* VS1 grounded, VS2 tied to CD2 */
140 /* VS1 tied to CD2, VS2 grounded */
143 /* VS1 float, VS2 grounded */
146 /* VS1 float, VS2 tied to CD2 */
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/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc286 * 5. Vector register numbers accessed by the segment load or store
289 static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
294 require_align(vs2, emul) &&
320 * register (vs2) group.
323 * the source vector register (vs2) group for
326 static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
331 bool ret = vext_check_st_index(s, vd, vs2, nf, eew) &&
339 if (seg_vd != vs2) {
340 ret &= require_noover(seg_vd, s->lmul, vs2, emul);
343 ret &= require_noover(seg_vd, s->lmul, vs2, emul);
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/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dpm8941.dtsi84 <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
224 interrupt-names = "ocp-5vs1", "ocp-5vs2";
233 pm8941_5vs1: 5vs1 {
243 pm8941_5vs2: 5vs2 {
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc424 * Sign extended from 5 bits: [-0x10, 0x0f].
535 TCGReg vs2, bool vm)
538 (vs2 & 0x1f) << 20 | (vm << 25);
687 * Vector registers uses the same 5 lower bits as GPR registers,
689 * With RVV 1.0, vs2 is the first operand, while rs1/imm is the
693 TCGReg vd, TCGReg vs2, TCGReg vs1)
695 tcg_out32(s, encode_v(opc, vd, vs1, vs2, true));
699 TCGReg vd, TCGReg vs2, TCGReg rs1)
701 tcg_out32(s, encode_v(opc, vd, rs1, vs2, true));
705 TCGReg vd, TCGReg vs2, int32_t imm)
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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dqcom,smd-rpm-regulator.yaml52 lvs3, 5vs1, 5vs2
68 l20, l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
110 "^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$":
H A Dqcom,spmi-regulator.yaml35 "^(5vs[1-2]|(l|s)[1-9][0-9]?|lvs[1-3])$":
157 "^vdd_s[1-5]-supply$": true
197 "^vdd_s[1-5]-supply$": true
235 - description: Over-current protection interrupt for 5V S1
236 - description: Over-current protection interrupt for 5V S2
239 - const: ocp-5vs1
240 - const: ocp-5vs2
324 "^vdd_s[1-5]-supply$": true
/openbmc/linux/drivers/regulator/
H A Dmt6358-regulator.c288 0, 1, 2, 4, 5, 9, 11, 13,
296 3, 4, 5, 6, 7, 9, 12,
304 2, 3, 5,
513 MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
591 MT6366_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
H A Dqcom_spmi-regulator.c252 SPMI_COMMON_IDX_MODE = 5,
279 #define SPMI_FTSMPS426_MODE_LPM_MASK 5
337 #define SPMI_FTSMPS_STEP_MARGIN_DEN 5
996 * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to in spmi_regulator_ult_lo_smps_set_voltage()
1640 SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0),
2229 { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", },
2230 { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", },
H A Dqcom_smd-regulator.c811 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
837 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
845 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
873 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm660_hfsmps, "vdd_s5" },
879 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_ht_nldo, "vdd_l5" },
906 { "l5", QCOM_SMD_RPM_LDOB, 5, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
921 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8226_hfsmps, "vdd_s5" },
926 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
959 { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
973 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_pldo, "vdd_l2_l5" },
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/openbmc/linux/arch/powerpc/crypto/
H A Dpoly1305-p10le_64.S17 # p = 2^130 - 5
32 # vs2 = [r2,.....]
35 # vs5 = [r1*5,...]
36 # vs6 = [r2*5,...]
37 # vs7 = [r2*5,...]
38 # vs8 = [r4*5,...]
42 # r0, r4*5, r3*5, r2*5, r1*5;
43 # r1, r0, r4*5, r3*5, r2*5;
44 # r2, r1, r0, r4*5, r3*5;
45 # r3, r2, r1, r0, r4*5;
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/openbmc/linux/tools/testing/selftests/powerpc/primitives/asm/
H A Dppc_asm.h80 ZEROIZE_GPRS(5, 12); \
169 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
573 #define cr5 5
627 #define fr5 5
662 #define v5 5
694 #define vs2 2
697 #define vs5 5
764 #define evr5 5
/openbmc/linux/arch/powerpc/include/asm/
H A Dppc_asm.h80 ZEROIZE_GPRS(5, 12); \
169 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
573 #define cr5 5
627 #define fr5 5
662 #define v5 5
694 #define vs2 2
697 #define vs5 5
764 #define evr5 5
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/pxaregs/pxaregs-1.14/
H A Dpxaregs.c57 { "ICR_SCLE", 0x40301690, 5, 1, 'x', " master clock enable " },
75 { "ISR_ALD", 0x40301698, 5, 1, 'x', " arbitration loss detected " },
93 { "PSSR_RDH", 0x40F00004, 5, 0x00000001, 'd', "PM receivers of all input GPIO are disabled" },
103 { "PWER_WE5", 0x40F0000C, 5, 0x00000001, 'd', "PM wake up due to GPIO 5 edge detect enabled" },
122 { "PRER_RE5", 0x40F00010, 5, 0x00000001, 'd', "PM wake up due to GPIO 5 rising edge detect enable…
140 { "PFER_FE5", 0x40F00014, 5, 0x00000001, 'd', "PM wake up due to GPIO 5 falling edge detect enabl…
158 { "PEDR_ED5", 0x40F00018, 5, 0x00000001, 'd', "PM wake up due to edge on GPIO 5 detected" },
181 { "PGSR_SS5", 0x40F00020, 5, 0x00000001, 'd', "PM GPIO pin 5 is driven to 1 during sleep" },
215 { "PGSR_SS37", 0x40F00024, 5, 0x00000001, 'd', "PM GPIO pin 37 is driven to 1 during sleep" },
249 { "PGSR_SS69", 0x40F00028, 5, 0x00000001, 'd', "PM GPIO pin 69 is driven to 1 during sleep" },
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